STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 16

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5432
When a bit of this register is at ”1”, the CAR1
Register bit which has the same number is
masked. The CAR1 bit which is masked do not
generate an interrupt.
9.6 CAR2: Complementary Alarm Register 2
7
SKIP
SLC
MFR
MFNR Multiframe Not recovered within 500 ms.
PRSR Pseudo Random Sequence Recovered.
PRSL Pseudo Random Sequence Lost.
9.7 CAMR2: Complementary Alarm Mask
7
This register can be read or written.
Bits: MMFNR, MMFR and MSKIP mask respectively
bit MFNR, MFR and SKIP when they are at ”1”.
16/46
1 MPRSL MPRSR MMFNR MMFR Nu
1
Register 2
PRSL PRSR MFNR MFR
SKIP.
After frame recovery, this bit is at ”1”
when an entire frame (32 words)
has been ignored or has been repeated
two times onto DOUT.
Slow Local Clock.
This bit does not generate interrupt.
When the value of this bit is 0, local clock
is faster than the remote clock.
When the value is ”1”, local clock is slower
than the remote clock (an entire frame has
been ignored).
Multiframe recovered within 400 ms.
After reframe time, if the multiframe is
recovered within 400 ms, MFR is set to ”1”.
After reframe time, the circuit researches
the multiframe during 500 milliseconds.
After this time, if the multiframe has not
been recovered, MFNR is set at ”1”. Then
the circuit is activated with the frame
recovery only, and the AX bit (bit 3 of the
odd Time Slot Zero transmitted) is set at ”0”.
When the PRS analyzer is validated (SAV
= 1), PRSR bit is set at ”1” if the synchro-
nization is performed.
PRSL, this bit is set to ”1” when PCR1/2
(PRS Counter Register) has reached 2
detected faults.
After Reset = FFH
After Reset = 80H
0
SLC
1 MSKIP
SKIP
14
0
0
9.8 FCR1: Fault Counter Register 1
7
F0/6
9.9 FCR2: Fault Counter Register 2
F7/13
If POL bit of CR2 register is at ”0”, the value of 14
bits fault counter is loaded into these registers
each second. If POL = 1, the registers are reset-
ted after each access. (POL indicates the differ-
ence between polling mode and interrupt mode,
see also CR2 register).
When the multiframe has not been recovered
within 400ms (MFNR = 1), these two registers in-
dicate the number of errored bits of Frame Align-
ment Signal received over one second period.
When the multiframe is recovered, these two reg-
isters indicate the number of errored CRC blocks
received over one second period.
9.10 ECR1: E Bit Counter Register 1
7
E 0/6
9.11 ECR2: E Bit Counter Register 2
7
E 7/13 7 most significant bits of the ECR counter
.
ECR1 and ECR2 are two registers associated to
ECR counter. Each second, the value of the
counter is loaded into these register (POL = 0).
When the multiframe is recovered, these two reg-
isters indicate the number of errored E bits re-
ceived over 1 second period.
1
7
1
1
1
F13
E13
E6
7 less significant bits of ECR counter
F6
7 less significant bits of the FCR counter.
7 most significant bits of the FCR counter.
F12
E12
F5
E5
After Reset = 80H
After Reset = 80H
After Reset = 80H
E11
F11
After Reset = 80H
E4
F4
E10
F10
F3
E3
F2
F9
E2
E9
F1
F8
E1
E8
E7
F0
F7
E0
0
0
0
0