STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 17

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

9.12 PCR1: PRS Counter Register 1
P0/6
9.13 PCR2: PRS Counter Register 2
P7/13 7 most significant bits of the PseudoRandom
PCR1 and PCR2 are two registers associated to
Pseudo Random Sequence Counter.
When the Pseudo Random Sequence Analyser is
validated, the counter indicates the number of er-
roneus bits received after the synchronisation of
the Pseudo Random Sequence.
9.14 ERTR: Error Rate Threshold Register
7
VT 0/3 Error Rate Validation Threshold of WER.
VT3
7
1
7
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P13
IT2
VT2
7 less significant bits of the Pseudo Random
Counter Register.
Counter Register.
VT0/3 bits give the threshold of activating
the indication of Alarm for erroneous Frame
Alignment words.
WER is set to ”1” only if the fault condition
is confirmed within the following 2 seconds.
P6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
P12
IT1
P5
VT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
After Reset = B8H
After Reset = 80H
P11
After Reset = 80H
IT0
P4
VT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P10
VT3
P3
words received during
Number of erroneous
Frame Alignement
VT2
2 seconds
P2
P9
16
18
20
22
24
26
28
30
32
36
40
44
48
52
56
60
VT1
P1
P8
VT0
P0
P7
0
0
0
IT 0/2 Error Rate Inhibition Threshold of WER
NB: If the threshold value of deactivating the indi-
cation of Alarm is superior to threshold value of
activating the indication of Alarm, then the value
of deactivating is irrelevant.
9.15 TS0RR: Time Slot Zero Received Register
7
Sa4R to Sa8R Bits 4 to 8 of the odd Time Slot
9.16 Sa6RR: Sa6 Bits Receive Register
7
Sa61R to Sa64R
These four bits are received from Sa6 subchan-
nel.
When a new word constituted by these four bits is
detected in accordance with SaT (CR6 Regis-
ters), a Sa6R interrupt is generated (a new word
can occur each millisecond).
Sa5R. Thisbit is the same asSa5R in TS0RR register.
AR
1
IT2
1
0
0
0
0
1
1
1
1
0
IT 0/2 bits give the threshold of deactivating
the indication of Alarm. Per default, WER is
set at ”0” when 12 or less erroneous
Frame Alignment Words are detected.
The Alarm deactivation requires the confir-
mation of the condition for the following 2 sec.
A bit received. It’s the same bit than the AR
bit of ALR register (see 9.2).
0
IT1
0
0
1
1
0
0
1
1
AR
0
Zero (Sa4 to Sa8) received from the
line. During reframe time, these bit
are at ”1”. Sa4R to Sa8R fix the
contentof TS0RR in accordancewith
CR8 Register and bit POLSa (CR6
register)
Sa5R Sa61R Sa62R Sa63R Sa64R
IT0
After Reset = 9FH
0
1
0
1
0
1
0
1
After Reset 80H
Sa4R Sa5R Sa6R Sa7R Sa8R
received during 2 seconds
Frame Alignment words
Number of erroneous
10
12
14
16
20
24
8
9
STLC5432
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0
0