STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 2

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5432
PIN DESCRIPTION
2/46
VCCD1
VCCD2
XTAL1
XTAL2
GNDD
GNDA
BRDO
VCCA
RCLO
BXDO
DOUT
Name
BRDI
RCLI
BXDI
HCR
LCR
DIN
L01
L02
LI1
LI2
VT
Pin
18
17
34
44
40
42
41
36
37
15
16
19
20
12
14
10
22
33
11
1
9
3
Type
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Positive power supply inputs for the digital (V
microprocessor interface signals (V
connected together.
Negative power supply pins which must be connected together close to the device. All
digital and analog signals are referred to these pins, which are normally at the system
ground.
Receive HDB3 signal differential inputs from the line transformer.
Positive power supply output for fixing reference voltage to the receive transformer.
Typical value is 2.375V
Transmit HDB3 signal differential outputs to the line transformer.When used with an
appropriate transformer, the line signal conforms to the output specifications in CCITT
with a nominal pulse amplitude of 3 volts for a 120 load on line side.
The master clock input which requires either a parallel resonance crystal to be tied
between this pin and XTAL2, or a clock input from a stable source. This clock does
not need to be synchronized to the system clock.
Crystal specifications = 32764 kHz
33pF to GND each side.
The output of the crystal oscillator, which should be connected to one end of the
crystal if used.
High clock received, bit clock. When the device has recovered the clock from the
HDB3 signal, HCR signal is synchronized to the remote circuit. The HCR frequency is
either 8192kHz if 8MCR bit of CR1 Register is put to 1 or 4096 kHz if 8MCR is set to
0.
Low clock received, frame clock. When the device has recovered the clock from the
HDB3 signal, LCR signal is synchronized to the remote entity.
The LCR frequency is 8 kHz if 8KCR bit is set to 1, or 4 kHz if 8KCR bit is set to 0.
When the remote clock is not recovered, HCR and LCR frequency are synchronized
to master clock (16384 kHz).
HCR and LCR can be used by the system in Terminal Mode.These two clocks can be
used by the transmit function of the device.
Binary Receive Data Output, 2048 kbit/s or 64kbit/s.
Receive Clock output, 2048 kHz or 64kHz.
After decoding, Binary Data and clock associated are provided for different
applications.
Binary Receive Data Input. 2048 kbit/s.
Receive Clock Input 2048 kHz.
Binary Transmit Data Output, 2048 kbit/s or output clock at 64kHz.
Before encoding Binary Data is provided to different applications (Optical Interface for
instance). Local clock is associated to this data.
This binary signal can replace BXD internal signal to be encoded if SELEX bit (CR1
Register) is set to 1.
Data Output. 30 B+D primary access data received from the line.Data can be shifted
out from the tristate output DOUT at the LCLK frequency on the rising edges during
all the time slots,except Time Slot Zero in accordance with TSOE bit (CR1Register).
NB : If parallel micro-interface is selected, DOUT is at high impedance after Reset.
DOUT is at low impedance after writing CR4 register.
Data Input : 30B+D primary access data to transmit to the line.Data can be shifted in
at the LCLK frequency on the falling edges during all the time slots, except Time Slot
Zero, in accordance with TSOE bit (CR1 Register).
CCD2
50 ppm parallel resonant; RS
Function
). They must be +5 Volts and must be directly
CCD1
) and analog (V
CCA
) sections and for
20
loaded with