STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 22

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5432
AVT
TABLE OF DIFFERENT LOCAL MULTIPLEX (with Parallel microprocessor interface only)
Ex : M2 = 1, M1 = 1, M0 = 0, each Multiplex includes 128 Time Slots, the data processed by the de-
vice during the internal time Slot 3 are the data connected to multiplexes during the external time slot
14 = 4 X 3 + 2.
22/46
M2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CONFIGURATION BITS
When DEL is at ”0”, Bit 0 of TS0
is indicated by the rising edge of Frame
synchronization signal.
When DEL is at ”1”, Bit 0 of TS0 is delayed;
the rising edge of Frame Synchronization
indicates the bit located just before Bit 0
Time Slot 0.
Adaptative Voltage Threshold Validation.
When AVT is at 1, the adaptive voltage
threshold is validated.
M1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
M0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
DCP
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Local Clock
LCLK in kHz
16384
16384
16384
16384
8192
8192
8192
2048
4096
4096
8192
4096
8192
8192
Data Rate in Kb/s
Multiplexes
EQV
2048
4096
8192
When AVT = 0, the adaptive function is not
validated; receiving is performed if the
attenuation of the signal is less than 6 dB.
Equalizer Validation.
When EQV is at ”1” internal equalizer is
validated (external capacitors are required
at the LI1 and LI2 inputs).
When EQV is at 0, the equalizer is never
operating (external capacitors are not
required).
Number of Time
Slots (TS)
1 X 32
2 X 32
4 X32
DIN
device 0
accordance with
the TSn of the
Time Slot in
TS 2n + 1
TS 4n + 1
TS 4n + 2
TS 4n + 3
DOUT
TS 2n
TS 4n
TSn
n
31