STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 25

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

9.32 TCR1: Test Configuration Register 1
7
GTS0 to GTS5 Time Slot associated to generator.
9.33 TCR2: Test Configuration Register 2
7
ATS0 to ATS5 Time Slot associated to Analyzer.
1
1
GTS5
ATS5
0
0
1
1
1
1
1
0
0
1
1
1
1
1
SGV GTS5 GTS4 GTS3 GTS2 GTS1 GTS0
SAV ATS5 ATS4 ATS3 ATS2 ATS1 ATS0
Sequence (PRBS). The internal analyzer
ATS4
GTS4
These 6 bits indicate Time Slot(s)
selected to transmit the Pseudo
Random Binary
These 6 bits indicate Time Slot(s)
selected to receive the Pseudo
Random Binary
0
X
0
0
0
1
1
0
X
0
0
0
1
1
After Reset = 80H
After Reset = 80H
ATS3
GTS3
0
X
0
0
0
1
1
X
0
0
0
0
1
1
ATS2
GTS2
X
0
0
0
0
1
1
X
0
0
0
0
1
1
GTS1
GTS1
0
0
0
X
0
0
1
1
1
X
0
0
0
1
1
1
SGV
SAV
GTS0
GTS0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
Sequence(PRBS) provided by the internal
generator (see Table).
Sequence Generator Validated.
When SGV is at ”1”, the generator provides
Pseudo Random Binary Sequence in
accordance with NX bit. When SGV is at 0,
the generator is not validated.
checks the sequence.
Sequence Analyzer Validated.
When SAV is at ”1”, the analyzer is
validated and the counter ECR1-ECR2
(14 bits) is associated to analyzer. The
length of PRBS is in accordance with NR
bit. After the sequence is recovered by the
analyzer. PRSR is set at ”1”
(Complementry Alarm
Register); the associated counter indicates
the number of faults received.
Time Slot(s) selected to receive PRBS
All the Time Slots except TS0
All the Time Slots including TS0
Not use
TS1
TS2
TS30
TS31
All the Time Slots except TS0
All the Time Slots including TS0
Not use
TS1
TS2
TS30
TS31
Time Slot(s) selected to transmit
PRBS
STLC5432
25/46