STLC5432Q STMICROELECTRONICS [STMicroelectronics], STLC5432Q Datasheet - Page 8

• Manufacturer Part Number: STLC5432Q
• Description: 2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5432
INTRODUCTION
This single chip CMOS Device interfaces the
physical multiplex of the application to the physi-
cal CEPT transmission link at 2048kb/s.
STLC5432 contains analog and digital functions
to implement line interface function and frame
synchronization. It meets pulse shape and jitter
specifications in accordance with CCITT Recom-
mendations and CEPT standards.
FUNCTIONAL DESCRIPTION
1. LINE INTERFACE
1.1 Receiver
The receive input signal should be derived via a
transformer of the same type used for the trans-
mit direction. The suggested transformer is the
VAC L4097-X004 or equivalent for the 75 ohms
case and the VAC 4097-X012 or equivalent for
the 120 ohms case. The electrical models of the
transformers are summarized in the following ta-
ble :
with:
Figure 2: Transmitter Diagram
8/46
Loads
n:
Ls:
120
( )
75
ENCODER
BIN/HDB3
1.57:1:1
2:1:1
n
( H)
Ls
0.3
0.2
SELEX
Winding ratioes
Leakage inductance
1
(pF)
Ck
15
15
BXDI BXDO
(mH)
Lh
2
2
1
LP2
1
Rcul
0.11
0.10
CLOCK
( )
RD RX
64KHz
SIG
TM
Rculll
1
0.23
0.20
( )
CRC4
Wiring between the transformer and the circuit
should respect the application schematic given in
annex. (see fig 4).
The internal fixed threshold is set to 200 mV over
the common mode voltage VCM (VCM = 2.375 V
nominal) to insure the specified transmission
range with a good noise immunity.
Two options are provided for special applications
requiring improved transmission ranges:
Ck:
Lh:
RcuI and RcuIII :
AUTO-ADAPTATIVE THRESHOLD:
Using the configuration register CR4 (AVT), a
peak amplitude detector circuit is connected to
the received signal and after digital processing,
an adaptative threshold value equal to 3/8 of
the peak value is obtained at the output of a D
to A converter and used for data detection.
AUTOMATIC EQUALIZER: connecting two ex-
ternal capacitors of 100pF in series between the
transformer and the circuits inputs, and using the
configuration register CR4 (EQV), the circuit will
select automatically a pre-compensation filter for
long line configuration (see application sche-
matic on figure 3 and 4 given in annex).
LP4
1
DOUT
RDS
GENERATOR
1
SGV
2 n -1
D
DATA IN CLOCK IS AT
CLOCK AT 2048KHz
64KHz, DATA OUT
ADAPTOR: WHEN
Inter winding capacitance
Principal inductance of
windings
DC resistances of
winding I and III.
SIG
1
BXDI
TSO
GENERATOR
1
TS
D93TL045B
DIN