AD9253-125EBZ AD [Analog Devices], AD9253-125EBZ Datasheet

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AD9253-125EBZ

Manufacturer Part Number
AD9253-125EBZ
Description
Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
Manufacturer
AD [Analog Devices]
Datasheet
Data Sheet
FEATURES
1.8 V supply operation
Low power: 110 mW per channel at 125 MSPS with scalable
SNR = 74 dB (to Nyquist)
SFDR = 90 dBc (to Nyquist)
DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
APPLICATIONS
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The
analog-to-digital converter (ADC) with an on-chip sample-
and-hold circuit designed for low cost, low power, small size,
and ease of use. The product operates at a conversion rate of
up to 125 MSPS and is optimized for outstanding dynamic
performance and low power in applications where a small
package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
power options
signal option (similar to IEEE 1596.3)
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
AD9253
is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS
Serial LVDS 1.8 V Analog-to-Digital Converter
Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
The
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
SENSE
RBIAS
VIN+A
VIN–A
VIN+B
VIN–B
AGND
VIN+C
VIN–C
VIN+D
VIN–D
VREF
VCM
AD9253
Small Footprint. Four ADCs are contained in a small, space-
saving package.
Low power of 110 mW/channel at 125 MSPS with scalable
power options.
Pin compatible to the
Ease of Use. A data clock output (DCO) operates at
frequencies of up to 500 MHz and supports double data
rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
AVDD
SELECT
SERIAL PORT
INTERFACE
REF
FUNCTIONAL BLOCK DIAGRAM
is available in a RoHS-compliant, 48-lead LFCSP.
PIPELINE
PIPELINE
PIPELINE
PIPELINE
ADC
ADC
ADC
ADC
1V
PDWN
©2011 Analog Devices, Inc. All rights reserved.
14
14
14
14
AD9633
SERIALIZER
SERIALIZER
AD9253
SERIALIZER
SERIALIZER
MANAGEMENT
Figure 1.
DIGITAL
DIGITAL
DIGITAL
DIGITAL
CLOCK
12-bit quad ADC.
DRVDD
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
AD9253
www.analog.com
D0+A
D0–A
D1+A
D1–A
D0+B
D0–B
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
D0+D
D0–D
D1+D
D1–D
DCO+
DCO–

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