PCA9545B NXP [NXP Semiconductors], PCA9545B Datasheet

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PCA9545B

Manufacturer Part Number
PCA9545B
Description
4-channel I2C-bus switch with interrupt logic and reset
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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PCA9545BPW
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PCA9545BPW
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1. General description
2. Features
The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the
I
individual SCx/SDx channel or combination of channels can be selected, determined by
the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one
for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND
of the four interrupt inputs.
An active LOW reset input allows the PCA9545A/45B/45C to recover from a situation
where one of the downstream I
LOW resets the I
does the internal power-on reset function.
The pass gates of the switches are constructed such that the V
the maximum high voltage which will be passed by the PCA9545A/45B/45C. This allows
the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of
the slave address.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any
PCA9545A/45B/45C
4-channel I
Rev. 07 — 19 June 2009
1-of-4 bidirectional translating switches
I
4 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I
Alternate address versions A, B and C allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
Channel selection via I
Power-up with all switch channels deselected
Low R
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
2
C-bus interface logic; compatible with SMBus standards
on
switches
2
C-bus state machine and causes all the channels to be deselected as
2
C-bus switch with interrupt logic and reset
2
C-bus, in any combination
2
C-buses is stuck in a LOW state. Pulling the RESET pin
2
C-bus
DD
pin can be used to limit
Product data sheet

Related parts for PCA9545B

PCA9545B Summary of contents

Page 1

... V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of the slave address. ...

Page 2

... Table 1. Type number PCA9545ABS PCA9545AD PCA9545APW PCA9545BPW PCA9545CPW 3.1 Ordering options Table 2. Type number PCA9545ABS PCA9545AD PCA9545APW PCA9545BPW PCA9545CPW PCA9545A_45B_45C_7 Product data sheet 4-channel I Ordering information Package Name Description HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 SO20 plastic small outline package ...

Page 3

... SD3 RESET SCL SDA INT0 to INT3 Fig 1. PCA9545A_45B_45C_7 Product data sheet 4-channel I PCA9545A/PCA9545B/PCA9545C SWITCH CONTROL LOGIC POWER-ON RESET INPUT FILTER Block diagram of PCA9545A/45B/45C Rev. 07 — 19 June 2009 PCA9545A/45B/45C 2 C-bus switch with interrupt logic and reset 2 I C-BUS CONTROL INTERRUPT LOGIC © ...

Page 4

... Pin configuration for HVQFN20 (transparent top view) Rev. 07 — 19 June 2009 PCA9545A/45B/45C 2 C-bus switch with interrupt logic and reset RESET 3 4 INT0 PCA9545APW 5 SD0 PCA9545BPW SC0 6 PCA9545CPW INT1 7 8 SD1 SC1 Fig 3. Pin configuration for TSSOP20 15 ...

Page 5

NXP Semiconductors 5.2 Pin description Table 3. Symbol A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 V SS INT2 SD2 SC2 INT3 SD3 SC3 INT SCL SDA V DD [1] HVQFN20 package die supply ground is connected to both ...

Page 6

... The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. The PCA9545BPW and PCA9545CPW are alternate address versions if needed for larger systems or to resolve conflicts. The data sheet will reference the PCA9545A, but the PCA9545B and PCA9545C function identically except for the slave address ...

Page 7

NXP Semiconductors 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9545A/45B/45C, which will be stored in the control register. If multiple bytes are received by the PCA9545A/45B/45C, it ...

Page 8

NXP Semiconductors 6.2.2 Interrupt handling The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9545A/45B/45C and the interrupt output will ...

Page 9

NXP Semiconductors 6.4 Power-on reset When power is applied to V PCA9545A/45B/45C in a reset condition until V reset condition is released and the PCA9545A/45B/45C registers and I machine are initialized to their default states (all zeroes) causing all the ...

Page 10

NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

Page 11

NXP Semiconductors 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ ...

Page 12

NXP Semiconductors 7.5 Bus transactions Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as shown in SDA START condition Fig 14. Write control register Data is read from PCA9545A/45B/45C using the Read mode as shown in ...

Page 13

NXP Semiconductors 8. Application design-in information 2 I C-bus/SMBus master (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a Fig 16. Typical application PCA9545A_45B_45C_7 Product data sheet 4-channel 2.7 ...

Page 14

NXP Semiconductors 9. Limiting values Table 6. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V (ground = 0 V). SS Symbol ...

Page 15

NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C; unless otherwise specified. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I ...

Page 16

NXP Semiconductors Table 8. Static characteristics +85 C; unless otherwise specified. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb ...

Page 17

NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t LOW ...

Page 18

NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 17. Definition of timing on the I SCL SDA RESET 50 % Fig 18. Definition of RESET timing START protocol condition (S) t SU;STA SCL t BUF ...

Page 19

NXP Semiconductors Fig 20. Expanded view of read input port register 12. Test information Fig 21. Test circuitry for switching times PCA9545A_45B_45C_7 Product data sheet 4-channel I SCL 2 1 SDA INPUT t v(INTnN INTN) INT V PULSE GENERATOR Definitions ...

Page 20

NXP Semiconductors 13. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 21

NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 22

NXP Semiconductors HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 0.85 mm terminal 1 index area terminal 1 20 index area DIMENSIONS (mm are ...

Page 23

NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction ...

Page 24

NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 25

NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 12. Acronym CDM DUT ESD HBM ...

Page 26

NXP Semiconductors 16. Revision history Table 13. Revision history Document ID Release date PCA9545A_45B_45C_7 20090619 • Modifications: Table 9 “Dynamic – Symbol t – Symbol C • Updated soldering information. PCA9545A_45B_45C_6 20070319 PCA9545A_45B_45C_5 20061017 PCA9545A_4 20060925 PCA9545A_3 20050303 (9397 750 ...

Page 27

NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 28

NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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