DAC104S085EVAL NSC [National Semiconductor], DAC104S085EVAL Datasheet - Page 6

• Manufacturer Part Number: DAC104S085EVAL
• Description: 10-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output
• Manufacturer: NSC [National Semiconductor]

www.national.com
f
t
SR
t
1/f
t
t
t
t
t
t
t
SCLK
s
WU
CH
CL
SS
DS
DH
CFSR
SYNC
Symbol
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release. The following specifica-
tions apply for V
12 to 1011. Boldface limits apply for T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified
Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input
current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the
operating ratings, or the power supply polarity is reversed).
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of V
if V
Note 8: To guarantee accuracy, it is required that V
Note 9: Typical figures are at T
Level).
Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
SCLK
A
is 3V, the digital input pins can be driven with a 5V logic device.
SCLK Frequency
Output Voltage Settling Time
(Note 10)
Output Slew Rate
Glitch Impulse
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Wake-Up Time
SCLK Cycle Time
SCLK High time
SCLK Low Time
SYNC Set-up Time prior to SCLK
Falling Edge
Data Set-Up Time prior to SCLK
Falling Edge
Data Hold Time after SCLK Falling
Edge
SCLK fall prior to rise of SYNC
SYNC High Time
A
= +2.7V to +5.5V, V
Parameter
J
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
JA
), and the ambient temperature (T
REFIN
MIN
A
and V
= V
≤ T
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
REFIN
100h to 300h code change
Code change from 200h to 1FFh
V
V
input frequency = 10kHz
V
V
A
A
REFIN
REFIN
A
A
, R
≤ T
= 3V
= 5V
be well bypassed.
L
MAX
= 2kΩ to GND, C
= 2.5V
= 2.5V
and all other limits are at T
Conductions
A
), and can be calculated using the formula P
±
±
6
0.1Vpp
0.1Vpp
L
= 200 pF to GND, f
20195304
A
, will not cause errors in the conversion result. For example,
A
= 25˚C, unless otherwise specified.
(Note 9)
Typical
160
4.5
0.5
0.8
0.5
1.5
1.5
40
12
70
25
SCLK
1
1
3
7
7
4
0
6
D
MAX = (T
= 30 MHz, input code range
(Note 9)
Limits
J
max − T
3.5
3.5
30
33
10
10
10
10
6
3
A
) / θ
JA
MHz (max)
µs (max)
. The values
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
(Limits)
nV-sec
nV-sec
nV-sec
nV-sec
Units
J
µsec
µsec
V/µs
kHz
max, the
dB