DAC1208D650HN NXP [NXP Semiconductors], DAC1208D650HN Datasheet - Page 67
DAC1208D650HN
Manufacturer Part Number
DAC1208D650HN
Description
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.DAC1208D650HN.pdf
(98 pages)
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NXP Semiconductors
Table 106. REINIT_CNTRL register (address 1Ch) bit description
Default settings are shown highlighted.
Table 107. PAGE_ADDRESS register (address 1Fh) bit description
DAC1208D650
Product data sheet
Bit
3
2
1
0
Bit
2 to 0
Symbol
RESYNC_O_L_LN3
RESYNC_O_L_LN2
RESYNC_O_L_LN1
RESYNC_O_L_LN0
Symbol
PAGE[2:0]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
Access
R/W
R/W
R/W
R/W
Access
R/W
2×, 4× or 8× interpolating DAC with JESD204A interface
Value
0
1
0
1
0
1
0
1
Value
0h
…continued
Description
lane 3, resync over link
lane 2, resync over link
lane 1, resync over link
lane 0, resync over link
Description
page_address
no action
lane 3 lane controller checks for
K28.5 /K/ symbols
no action
lane 2 lane controller checks for
K28.5 /K/ symbols
no action
lane 1 lane controller checks for
K28.5 /K/ symbols
no action
lane 0 controller checks for K28.5 /K/ symbols
DAC1208D650
© NXP B.V. 2010. All rights reserved.
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