DAC121S101QML_10 NSC [National Semiconductor], DAC121S101QML_10 Datasheet - Page 16

• Manufacturer Part Number: DAC121S101QML_10
• Description: 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output
• Manufacturer: NSC [National Semiconductor]

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1.0 Functional Description
1.1 DAC SECTION
The DAC121S101 is fabricated on a CMOS process with an
architecture that consists of switches and a resistor string that
are followed by an output buffer. The power supply serves as
the reference voltage. The input coding is straight binary with
an ideal output voltage of:
where D is the decimal equivalent of the binary code that is
loaded into the DAC register and can take on any value be-
tween 0 and 4095.
1.2 RESISTOR STRING
The simplified resistor string is shown in
ally, this string consists of 4096 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. This configuration guarantees that the DAC is
monotonic.
FIGURE 3. DAC Resistor String
V
OUT
= V
A
x (D / 4096)
Figure
FIGURE 4. Input Register Contents
3. Conceptu-
30018007
16
1.3 OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an
output voltage range of 0V to V
rail types, exhibit a loss of linearity as the output approaches
the supply rails (0V and V
linearity is specified over less than the full output range of the
DAC. The output capabilities of the amplifier are described in
the Electrical Tables.
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs. See the Timing Diagram
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the D
bit serial input register on the falling edges of SCLK. On the
16th falling clock edge, the last data bit is clocked in and the
programmed function (a change in the mode of operation and/
or a change in the DAC register contents) is executed. At this
point the SYNC line may be kept low or brought high. In either
case, it must be brought high for the minimum specified time
before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and D
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register,
two bits are "don't cares" and are followed by two bits that
determine the mode of operation (normal mode or one of
three power-down modes). The contents of the serial input
register are transferred to the DAC register on the sixteenth
falling edge of SCLK. See Timing Diagram,
IN
buffers draw more current when they
Figure
30018008
A
, in this case). For this reason,
A
IN
4, has sixteen bits. The first
. All amplifiers, even rail-to-
line is clocked into the 16-
Figure
2.