ISL70001SRHF INTERSIL [Intersil Corporation], ISL70001SRHF Datasheet
ISL70001SRHF
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ISL70001SRHF Summary of contents
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Rad Hard and SEE Hard 6A Synchronous Buck Regulator ISL70001SEH The ISL70001SEH is a radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulator with integrated MOSFETs. This single chip power solution operates over an input voltage range of ...
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... TB363. 2 ISL70001SEH POWER-ON RESET (POR) SLOPE COMPENSATION PWM CONTROL EA GM LOGIC COMPENSATION UV POWER-GOOD PART NUMBER (Note 2) ISL70001SEHVF (Note 1) ISL70001SEHVX ISL70001SRHF/PROTO (Note 1) ISL70001SRHX/SAMPLE Evaluation Board PVINx CURRENT SENSE GATE LXx DRIVE PGNDx TDI BIT TDO TRIM ZAP TRIM TEMP. RANGE (°C) PACKAGE ...
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Pin Configuration M/S ZAP TDI TDO PGOOD SS DVDD DVDD DGND DGND AGND AGND Pin Descriptions PIN NUMBER PIN NAME 1, 2, 27, 28, 29, 30, PGNDx These pins are the power grounds associated with the corresponding internal power blocks. ...
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Pin Descriptions (Continued) PIN NUMBER PIN NAME 12 SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation where: t ...
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Typical Application Schematic PVIN1 5V PVIN2 100µF 1µF PVIN3 PVIN4 PVIN5 1µF PVIN6 1 AVDD 1µF AGND 1 DVDD 1µF VSENSE DGND EN 10nF M/S PORSEL TDI TDO ZAP FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION 5 ...
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Typical Application Schematic PVIN1 3.3V PVIN2 100µF 1µF PVIN3 PVIN4 PVIN5 1µF PVIN6 1 DVDD 1µF DGND 1 AVDD 1µF VSENSE AGND EN M/S 10nF PORSEL TDI TDO ZAP FIGURE 4. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION 6 ...
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Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V 0.65V; PORSEL = ...
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Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = 5.5V; GND = AGND = DGND = PGNDx = TDI = TDO = ZAP = 0V 0.65V; PORSEL = ...
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Functional Description The ISL70001SEH is a monolithic, fixed frequency, current-mode synchronous buck regulator with user configurable power blocks. Two ISL70001SEH devices can be used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs and CPUs. The ISL70001SEH utilizes peak ...
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To run the regulator from the internal oscillator, connect the M/S pin to DVDD. In this case, the output of the internal oscillator appears on the SYNC pin. To synchronize the regulator to the SYNC output of another ISL70001SEH regulator ...
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The soft-start capacitor is charged by an internal I source. As the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. Once the voltage on the SS ...
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R is load resistance and C is the output load O OUT capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. Figure 9 shows a Type 2 amplifier and its response, along with the ...
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Another stability requirement on the selection of the output capacitor is that the ‘ESR zero’ placed at 60kHz to ZESR 90kHz. This range is set by an internal, single compensation zero at 8.6kHz. This ESR zero location ...
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PCB Design PCB design is critical to high-frequency switching regulator performance. Careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. Selection of a suitable thermal interface material is also required for optimum ...
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Die Characteristics Die Dimensions 5720µm x 5830µm (225.2 mils x 229.5 mils) Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil) Interface Materials GLASSIVATION Type: Silicon Oxide and Silicon Nitride Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm TOP METALLIZATION ...
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PAD NAME PAD NUMBER AVDD 15 REF PORSEL 19 PVIN6 20 LX6 21 PGND6 22 PGND5 23 LX5 24 PVIN5 25 PVIN4 26 LX4 27 PGND4 28 PGND3 29 LX3 30 PVIN3 31 PVIN2 32 ...
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Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION November 30, 2011 FN7956.0 Initial Release ...