ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet
ADSP-BF533
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ADSP-BF533 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. ADSP-BF531/ADSP-BF532/ADSP-BF533 External Memory Controller with glueless support for SDRAM, SRAM, FLASH, and ROM Flexible memory booting options from SPI and external ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 TABLE OF CONTENTS General Description ................................................. 3 Portable Low Power Architecture ............................. 3 System Integration ................................................ 3 ADSP-BF531/2/3 Processor Peripherals ..................... 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 4 DMA Controllers .................................................. 8 Real-Time Clock ................................................... 8 Watchdog Timer .................................................. 9 Timers ............................................................... 9 Serial Ports (SPORTs) ............................................ 9 Serial Peripheral Interface (SPI) Port ......................... 9 UART Port ........................................................ 10 Programmable Flags (PFx) .................................... 10 Parallel Peripheral Interface ................................... 10 Dynamic Power Management ...
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... The ADSP-BF531/2/3 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configura- tions are shown in Table 1. Table 1. Processor Comparison ADSP-BF531 ADSP-BF532 ADSP-BF533 Maximum 400 MHz 400 MHz Performance 800 MMACs 800 MMACs ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 saturation and rounding, and sign/exponent detection. The set of video instructions includes byte alignment and packing oper- ations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. ...
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... ASYNC MEMORY BANK 2 (1M BYTE) 0x2020 0000 ASYNC MEMORY BANK 1 (1M BYTE) 0x2010 0000 ASYNC MEMORY BANK 0 (1M BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE TO 128M BYTE) 0x0000 0000 Figure 3. ADSP-BF533 Internal/External Memory Map ADSP-BF531/ADSP-BF532/ADSP-BF533 ADDRE SS ARITHMETIC UNIT DAG0 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 0xFFFF FFFF CORE MMR REGISTERS (2M BYTE) 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM (4K BYTE) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM / CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION SRAM (16K BYTE) 0xFFA0 8000 ...
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... A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 3. System Interrupt Controller (SIC) EVT Entry Peripheral Interrupt Event ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 • Clocking – Each transmit and receive port can either use an external serial clock or generate its own, in frequencies ranging from (f • ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. UART PORT The ADSP-BF531/2/3 processor provides a full-duplex Univer- sal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs ...
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... PLL is bypassed, the processor’s core clock (CCLK) and sys- tem clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, ADSP-BF531/ADSP-BF532/ADSP-BF533 although the changes are not realized until the Full-On mode is entered. DMA access is available to appropriately configured L1 memories ...
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... This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. * See EE-228: Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors. Rev Page March 2004 is the duration running at f ...
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... All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed ADSP-BF531/ADSP-BF532/ADSP-BF533 into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 The BMODE pins of the Reset Configuration Register, sampled during power-on resets and software-initiated resets, imple- ment the following modes: • Execute from 16-bit external memory – Execution starts from address 0x2000 0000 with 16-bit packing. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3-cycle hold time ...
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... Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF531/2/3 processor to monitor and control the target board processor during emulation. The emu- ADSP-BF531/ADSP-BF532/ADSP-BF533 lator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non- intrusive in-circuit emulation is assured by the use of the processor’ ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 PIN DESCRIPTIONS ADSP-BF531/2/3 processor pin definitions are listed in All pins are three-stated during and immediately after reset, except the Memory Interface, Asynchronous Memory Control, and Synchronous Memory Control pins, which are driven high active, then the memory pins are also three-stated. All ...
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... SPI Port MOSI I/O Master Out Slave In 7 MISO I/O Master In Slave Out SCK I/O SPI Clock ADSP-BF531/ADSP-BF532/ADSP-BF533 PPI Clock SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary SPORT1 Receive Data Primary SPORT1 Receive Data Secondary ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 9. Pin Descriptions (Continued) Pin Name I/O Function UART Port Real Time Clock 8 RTXI I RTXO O JTAG Port TCK I TDO O TDI I TMS I 9 TRST I EMU O Clock CLKIN I XTAL O Mode Controls RESET I 8 NMI I BMODE1–0 I Voltage Regulator VROUT1–0 O Supplies ...
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... IN 1 Applies to output and bidirectional pins. 2 Applies to input pins except JTAG inputs. 3 Applies to JTAG input pins (TCK, TDI, TMS, TRST). 4 Applies to three-statable pins. 5 Applies to all signal pins. 6 Guaranteed, but not tested. ADSP-BF531/ADSP-BF532/ADSP-BF533 =maximum DDEXT =maximum DDEXT =minimum DDEXT ...
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... DDINT External (I/O) Supply Voltage (V ) DDEXT Input Voltage Output Voltage Swing Load Capacitance ADSP-BF533 Core Clock (CCLK) ADSP-BF532/BF531 Core Clock (CCLK) Peripheral Clock (SCLK) Storage Temperature Range Junction Temperature Under Bias ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... Core Cycle Period (V =0.9 V–5%) CCLK DDINT t Core Cycle Period (V =0.8 V) CCLK DDINT t System Clock Period SCLK Table 11. Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500 Parameter t Core Cycle Period (V =1.2 V–5%) CCLK DDINT t Core Cycle Period (V =1.1 V–5%) CCLK DDINT ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Clock and Reset Timing Table 15 and Figure 10 describe clock and reset operations. Per Absolute Maximum Ratings on Page 20, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz. Table 15. Clock and Reset Timing Parameter Timing Requirements t CLKIN Period ...
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... Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE. SETUP 2 CYCLES CLKOUT t DO AMSx ABE1–0 ADDR19–1 AOE ARE ARDY DATA15–0 ADSP-BF531/ADSP-BF532/ADSP-BF533 1 1 PROGRAMMED READ ACCESS 4 CYCLES BE, ADDRESS HARDY t SARDY Figure 11. Asynchronous Memory Read Cycle Timing Rev ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Asynchronous Memory Write Cycle Timing Table 17. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements t ARDY Setup Before CLKOUT SARDY t ARDY Hold After CLKOUT HARDY Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT t Output Delay After CLKOUT ...
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... Data Disable After CLKOUT DSDAT t Data Enable After CLKOUT ENSDAT 1 For V = 1.2 V. DDINT 2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. CLKOUT DATA (IN) DATA(OUT) CMND ADDR (OUT) ADSP-BF531/ADSP-BF532/ADSP-BF533 SCLK t SSDAT t HSDAT t DCAD t ENSDAT t DCAD t HCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 External Port Bus Request and Grant Cycle Timing Table 19 and Figure 14 describe external port bus request and bus grant operations. Table 19. External Port Bus Request and Grant Cycle Timing , 1, 2 Parameter Timing Requirements t BR Asserted to CLKOUT High Setup BS t CLKOUT High to BR Deasserted Hold Time ...
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... Internal Frame Sync Delay After PPI_CLK DFSPE t Internal Frame Sync Hold After PPI_CLK HOFSPE t Transmit Data Delay After PPI_CLK DDTPE t Transmit Data Hold After PPI_CLK HDTPE 1 PPI_CLK frequency cannot exceed f /2 SCLK ADSP-BF531/ADSP-BF532/ADSP-BF533 DRIVE SAMPLE EDGE t PCLKW PPI_CLK t DFSPE t t HOFSPE SFSPE PPI_FS1 PPI_FS2 ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Serial Ports Table 21 through Table 26 on Page 29 and through Figure 18 on Page 32 describe Serial Port operations. Table 21. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TSCLK/RSCLK SFSE t TFS/RFS Hold After TSCLK/RSCLK HFSE t Receive Data Setup Before RSCLK SDRE ...
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... Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0 DDTLFSE t Data Enable from late FS or MCE = 1, MFD = 0 DTENLFSE 1 MCE = 1, TFS enable and TFS valid follow t DDTENFS 2 If external RFS/TFS setup to RSCLK/TSCLK > t ADSP-BF531/ADSP-BF532/ADSP-BF533 1,2 and t . DDTLFSE /2, then t and t apply ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE t SCLKIW RSCLK t DFSE t t HOFSE SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DRIVE EDGE t SCLKIW TSCLK t DFSI t t HOFSI ...
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... DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE TSCLK t SFSE/I TFS t DDTENFS DT 1ST BIT t DDTLFSE Figure 17. External Late Frame Sync (Frame Sync Setup < t Rev Page March 2004 ADSP-BF531/ADSP-BF532/ADSP-BF533 DRIVE t HOFSE/I t DDTE/I HDTE/I 2ND BIT DRIVE t HOFSE/I t DDTE/I t HDTE/I 2ND BIT /2) SCLKE ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 EXTERNAL RFS WITH MCE = 1, MFD = 0 RSCLK RFS DT LATE EXTERNAL TFS TSCLK TFS DT DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DTENLSCK 1ST BIT t DDTLSCK DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE DTENLSCK HDTE/I 1ST BIT t DDTLSCK Figure 18. External Late Frame Sync (Frame Sync Setup > t Rev ...
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... SCK (CPOL = 1) (OUTPUT) MOSI (OUTPUT) CPHA=1 t SSPIDM MISO (INPUT) MOSI MSB (OUTPUT) CPHA=0 t SSPIDM MISO MSB VALID (INPUT) ADSP-BF531/ADSP-BF532/ADSP-BF533 t SPICHM SPICLM t SPICLM SPICHM t t DDSPIDM HDSPIDM MSB t t HSPIDM MSB VALID t DDSPIDM t HSPIDM LSB VALID Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing Rev ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Serial Peripheral Interface (SPI) Port —Slave Timing Table 28 and Figure 20 describe SPI port slave operations. Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter Timing Requirements t Serial Clock High Period SPICHS t Serial Clock low Period SPICLS t Serial Clock Period SPICLK ...
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... RXD RECEIVE INTERNAL UART RECEIVE INTERRUPT TXD TRANSMIT INTERNAL UART TRANSMIT INTERRUPT ADSP-BF531/ADSP-BF532/ADSP-BF533 Figure 21 DATA(5–8) START DATA(5–8) Figure 21. UART Port—Receive and Transmit Timing Rev Page March 2004 STOP UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ STOP (1– ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Programmable Flags Cycle Timing Table 29 and Figure 22 describe programmable flag operations. Table 29. Programmable Flags Cycle Timing Parameter Timing Requirements t Flag Input Pulse Width WFI Switching Characteristics t Flag Output Delay from CLKOUT Low DFO CLKOUT PF (OUTPUT) PF (INPUT) t DFO FLAG OUTPUT t WFI FLAG INPUT Figure 22 ...
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... The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode. 2 The minimum time for t is one cycle, and the maximum time for t HTO CLKOUT TMRx (PWM OUTPUT MODE) TMRx (WIDTH CAPTURE AND EXTERNAL CLOCK MODES) ADSP-BF531/ADSP-BF532/ADSP-BF533 1 (Measured in SCLK Cycles) 1 (Measured in SCLK Cycles) 2 (Measured in SCLK Cycles) 32 equals (2 –1) cycles. HTO ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 JTAG Test And Emulation Port Timing Table 31 and Figure 24 describe JTAG port operations. Table 31. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... SOURCE VOLTAGE (V) Figure 25. Drive Current A (Low V 150 100 50 0 –50 –100 –150 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 26. Drive Current A (High V ADSP-BF531/ADSP-BF532/ADSP-BF533 V DDEXT = 2.25V @ 95 ° DDEXT = 2.50V @ 25 ° DDEXT = 2.75V @ –40 ° C –100 –150 2.0 2.5 3.0 150 100 ) DDEXT V DDEXT = 2.95V @ 95 ° DDEXT = 3.30V @ 25 ° ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 –20 –40 –60 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 29. Drive Current C (Low –20 –40 –60 –80 –100 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 30. Drive Current C (High V 100 80 ° DDEXT = 2.25V @ DDEXT = 2.50V @ 25 ° 2.75V @ –40 ° DDEXT ...
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... I 50 DDHIBERNATE DDRTC 1 See EE-229: Estimating Power for ADSP-BF533 Blackfin Processors data is specified for typical process parameters. All data at 25º Processor executing 75% dual Mac, 25% ADD with moderate data bus activity. 4 See the ADSP-BF53x Blackfin Processor Hardware Reference Manual for defini- tions of Sleep and Deep Sleep operating modes ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 TEST CONDITIONS All timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving ...
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... RISE TIME 100 150 LOAD CAPACITANCE (PF) Figure 37. Typical Output Delay or Hold for Driver A at EVDD ADSP-BF531/ADSP-BF532/ADSP-BF533 CLKOUT (CLKOUT DRIVER), EVDD MIN = 2.25V, TEMPERATURE = 85° FALL TIME 200 250 Figure 38. Typical Output Delay or Hold for Driver B at EVDD MIN CLKOUT (CLKOUT DRIVER), EVDD MAX = 3.65V, TEMPERATURE = 85° ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 TMR0 (33 MHZ DRIVER), EVDD MIN = 2.25V, TEMPERATURE = 85° RISE TIME 100 LOAD CAPACITANCE (PF) Figure 40. Typical Output Delay or Hold for Driver C at EVDD TMR0 (33 MHZ DRIVER), EVDD MAX = 3.65V, TEMPERATURE = 85° RISE TIME ...
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... Table 34. Thermal Characteristics for ST-176-1 Package Parameter Condition 0 Linear m/s Airflow JA 1 Linear m/s Airflow JMA 2 Linear m/s Airflow JMA 0 Linear m/s Airflow JT 1 Linear m/s Airflow JT 2 Linear m/s Airflow JT ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 35. Thermal Characteristics for B-169 Package Parameter JA JMA P D JMA for can be used for a first P D ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 160-LEAD BGA PINOUT Table 36 lists the BGA pinout by signal. lists the BGA pinout by ball number. Table 36. 160-Ball BGA Pin Assignment (Alphabetically by Signal) Signal Ball No. Signal ABE0 H13 DATA12 ABE1 H12 DATA13 ADDR1 J14 DATA14 ADDR10 M13 DATA15 ADDR11 M14 DATA2 ...
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... PPI_CLK G11 C10 RESET G12 C11 GND G13 C12 VDDEXT G14 Figure 44 lists the top view of the BGA ball configuration. Figure 45 lists the bottom view of the BGA ball configuration. ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 36 on Signal Ball No. SMS H1 SCAS H2 SCK H3 PF0 H4 MOSI H11 GND ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 KEY: V GND DDINT V I/O DDEXT Figure 44. 160-Ball BGA Ball Configuration (Top View KEY: V GND DDINT V I/O DDEXT Figure 45. 160-Ball BGA Ball Configuration (Bottom View ...
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... EVDD BR C17 EVDD CLKIN A14 GND CLKOUT D16 GND DATA [0] U14 GND DATA [1] T12 GND DATA [10] T8 GND DATA [11] U8 GND ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 39 on Page 52 Ball No. Signal Ball No. T7 GND G11 U6 GND H7 T6 GND H8 U13 GND H9 T11 GND H10 U12 GND ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 39 lists the PBGA pinout by ball number. Page 51 lists the PBGA pinout by signal. Table 39. 169-Ball PBGA Pin Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal A1 PF [4] D16 CLKOUT A2 PF [5] D17 AMS [ [7] E1 MOSI A4 PF [9] E2 MISO A5 PF [11] E16 AMS [1] ...
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... BMODE0 96 GND BMODE1 95 GND BR 163 GND CLKIN 10 GND CLKOUT 169 GND DATA0 116 GND DATA1 115 GND DATA10 103 GND ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 41 on Page 52 Lead No. Signal Lead No. 102 GND 88 101 GND 89 100 GND 90 99 GND 91 98 GND 92 114 GND 97 113 GND ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 Table 41 lists the LQFP pinout by lead number. Page 51 lists the LQFP pinout by signal. Table 41. 176-Lead LQFP Pin Assignment (Numerically by Lead Number) Lead No. Signal Lead No. 1 GND 41 2 GND 42 3 GND 43 4 VROUT2 44 5 VROUT1 45 6 VDDEXT 46 7 GND 47 8 GND ...
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... Figure 47—176-LEAD LQFP (ST-176-1) and Figure 48—169-Ball Plastic Ball Grid Array, mini-BGA (B-169) are shown in millimeters. BALL A1 INDICATOR 1.70 MAX NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION AE. 3. MINIMUM BALL HEIGHT 0.25. ADSP-BF531/ADSP-BF532/ADSP-BF533 12.00 BSC 10.40 BSC SQ TOP VIEW 1.31 1.21 1.11 DETAIL A SEATING PLANE ...
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... ADSP-BF531/ADSP-BF532/ADSP-BF533 0.27 0.22 0.17 SEATING PLANE 0.08 MAX LEAD COPLANARITY 0.15 0.05 NOTES 1. DIMENSIONS IN MILLIMETERS 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL 0.75 0.60 0.45 176 1 PIN 1 1. 1.40 1.35 1.60 MAX DETAIL A DETAIL A Figure 47. 176-LEAD LQFP (ST-176-1) Rev Page March 2004 26 ...
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... TOP VIEW SIDE VIEW DETAIL A NOTES 1. DIMENSIONS ARE IN MILLIMETERS. 2. COMPLIES WITH JEDEC REGISTERED OUTLINE MS-034, VARIATION AAG MINIMUM BALL HEIGHT 0.40 Figure 48. 169-Ball Plastic Ball Grid Array, mini-BGA (B-169) Rev Page March 2004 ADSP-BF531/ADSP-BF532/ADSP-BF533 BOTTOM VIEW 16.00 BSC SQ 1.00 BSC BALL PITCH ...
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... Temperature Range (Ambient ) ADSP-BF533SKBC600 0ºC to 70ºC ADSP-BF533SBBC500 –40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 500 MHz 1 ADSP-BF533SBBZ500 –40ºC to 85ºC Plastic Ball Grid Array (PBGA) B-169 ADSP-BF532SBBC400 –40ºC to 85ºC Chip Scale Package Ball Grid Array (mini-BGA) BC-160 400 MHz ADSP-BF532SBST400 – ...