EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 287
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 287 of 396
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PS019209-0504
EMAC PHY Unit Select Address Register
The EMAC PHY Unit Select Address Register allows the selection of multiple con-
nected external PHY devices. See Table 158.
Table 158. EMAC PHY Unit Select Address Register
(EMAC_FIAD = 003Fh)
EMAC Transmit Polling Timer Register
This register sets the Transmit Polling Period in increments of TPTMR =
SYSCLK ÷ 256. Whenever this register is written, the status of the Transmit Buffer
Descriptor is checked to determine if the EMAC owns the Transmit buffer. It then
rechecks this status every TPTMR (calculated by TPTMR * EMAC_PTMR[7:0]).
The Transmit Polling Timer is disabled if this register is set to
ables the transmitting of packets). If a transmission is in progress when
EMAC_PTMR is set to
Table 159. EMAC Transmit Polling Timer Register
(EMAC_PTMR = 0040h)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:5]
[4:0]
FIAD
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
EMAC_PTMR
Value
000
00h–
1Fh
Value
00h–
FFh
00h
Description
Reserved.
Programmable 5-bit value that selects an external PHY.
R/W
Description
The Transmit polling period.
P R E L I M I N A R Y
R
7
0
7
0
, the transmission will complete. See Table 159.
R/W
R
6
0
6
0
R/W
R
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
Ethernet Media Access Controller
3
0
3
0
Product Specification
R/W
R/W
00h
2
0
2
0
(which also dis-
eZ80F91 MCU
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
268
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