EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 96
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 96 of 396
- Download datasheet (5Mb)
PS019209-0504
Caution:
WAIT Input Signal
Similar to the programmable wait states, an external peripheral can drive the
WAIT input pin to force the CPU to provide additional clock cycles to complete its
Read or Write operation. Driving the WAIT pin Low stalls the CPU. The CPU
resumes operation on the first rising edge of the internal system clock following
deassertion of the WAIT pin.
Figure 7. Wait Input Sampling Block Diagram
An example of wait state operation is illustrated in Figure 8. In this example, the
Chip Select is configured to provide a single wait state. The external peripheral
being accessed drives the WAIT pin Low to request assertion of an additional wait
state. If the WAIT pin is asserted for additional system clock cycles, wait states
are added until the WAIT pin is deasserted (active High).
Wait
Pin
If the WAIT pin is to be driven by an external device, the corresponding Chip Select for
the device must be programmed to provide at least one wait state. Due to input sampling
of the WAIT input pin (shown in Figure 7), one programmable wait state is required to
allow the external peripheral sufficient time to assert the WAIT pin. It is recommended
that the corresponding Chip Select for the external device be programmed to provide the
maximum number of wait states (seven).
System Clock
D
Q
P R E L I M I N A R Y
eZ80
CPU
Chip Selects and Wait States
Product Specification
eZ80F91 MCU
77
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