KSZ8862-16_10 MICREL [Micrel Semiconductor], KSZ8862-16_10 Datasheet - Page 33
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KSZ8862-16_10
Manufacturer Part Number
KSZ8862-16_10
Description
2-Port Ethernet Switch with Non-PCI Interface and Fiber Support
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
1.KSZ8862-16_10.pdf
(125 pages)
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8862M
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, then the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, then the carrier sense type backpressure is reactivated
again until switch resources free up. If a collision occurs, then the binary exponential back-off algorithm is skipped and
carrier sense is generated immediately, thus reducing the chance of further collisions and carrier sense is maintained to
prevent packet reception.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half-duplex modes, the user must enable the following:
1. Aggressive back off (bit 8 in SGCR1)
2. No excessive collision drop (bit 3 in SGCR2)
Note: These bits are not set in default, since this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8862M has an intelligent option to protect the switch system from receiving too many broadcast packets. As the
broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth
and available space in transmit queues) may be utilized. The KSZ8862M has the option to include “multicast packets” for
storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per
port basis in P1CR1 [7] and P2CR1 [7]. The rate is based on a 67ms interval for 100BT and a 670ms interval for 10BT. At
the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of
bytes during the interval. The rate definition is described in SGCR3 [2:0] [15:8]. The default setting is 0x63 (99 decimal).
This is equal to a rate of 1%, calculated as follows:
Note: 148,800 frames/sec is based on 64-byte block of packets in 100BASE-T with 12 bytes of IPG and 8 bytes of
preamble between two packets.
Clock Generator
The X1 and X2 pins are connected to a 25 MHz crystal. X1 can also serve as the connector to a 3.3V, 25 MHz oscillator
(as described in the pin description).
The bus interface unit (BIU) uses BCLK (Bus Clock) for synchronous accesses. The maximum host port frequency is 50
MHz for VLBus-like and burst mode (32-bit interface only).
Bus Interface Unit (BIU)
The host interface of the BIU is designed to communicate with embedded processors. The host interface of the
KSZ8862M is a generic bus interface. Some glue logic may be required when the interface talks to various buses and
processors.
In terms of transfer type, the BIU can support two transfers: asynchronous transfer and synchronous transfer. To support
these transfers (asynchronous and synchronous), the BIU provides three groups of signals:
Since both synchronous and asynchronous signals are independent of each other, synchronous burst transfer and
asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of the common signals).
In terms of physical data bus size, the KSZ8862M supports 8, 16, and 32 bit host/industrial standard data bus sizes.
Given a physical data bus size, the KSZ8862M supports 8, 16, or 32-bit data transfers depending upon the size of the
physical data bus. For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8862-
32MQL); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (KSZ8862-16MQL); and for 8-bit
system/host data bus, it only allows 8-bit data transfers (KSZ8862-16MQL).
Note that KSZ8862M does not support internal data byte-swap but it does support internal data word-swap. This means
that the system/host data bus HD [7:0] has to connect to both D [7:0] and D [15:8] for 8-bit data bus interfaces. However,
the system/host data bus HD [15:8] and HD [7:0] just connects to D [15:8] and D [7:0], respectively, for 16-bit data bus
interface; there is no need to connect HD [31:24] and HD [23:16] to D [31:24] and D [23:16].
Micrel, Inc.
August 2010
1. Synchronous signals
2. Asynchronous signals
3. Common signals used for both synchronous and asynchronous transfers.
148,800 frames/sec X 67 ms/interval X 1% = 99 frames/interval (approx.) = 0x63
33
KSZ8862-16/32MQL
M9999-081310-3.1