CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 196

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

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27.0 Revision History
10/14/02
10/16/02
11/11/02
11/21/02
Date
A22 ('13 only)
Bus State
WR[1:0]
A[21:0]
D[15:0]
(y ≠ x)
(y ≠ x)
SELx
SELy
CLK
RD
Original release of full CP3UB17 datasheet.
Corrections to flash memory programming
sequence and MFT block diagrams.
Numerous minor corrections. Added more
description to AAI section. Added external
reset circuit. Fixed problems with figures.
Converted to new data sheet format.
Removed TB functionality from MFT
section.
Table 65 Revision History
Major Changes From Previous Version
T
idle
t
t
5
5
, t
, t
12
12
t
4
Figure 81. Early Write Between Fast Read Cycles
Fast Read
T1-2
t
In
1
t
2
T1
t
t
t
4
5
5
, t
, t
, t
12
12
12
196
Early Write
1/13/03
5/20/03
T2
Date
Out
Table 65 Revision History (Continued)
Removed erroneous warning to always
write the IOCFG register with bit 1 set.
Alternate clock source for Advanced Audio
Interface changed to Aux1 clock. Changed
warning about clock glitches to say
Microwire interface must be disabled when
modifying bits in MWCTL1 register.
Changed bit settings which occur in step 2
of the sequence of ACCESS.bus slave
mode address match or global match.
Timer Mode Control Register bit 3 is
reserved and bit 2 is TAEDG. Bit 7 is the
TEN bit (a bit description has been added).
Polarity of all of the bits in the INTCTL
register has been inverted.
Updated DC specifications. Fixed errors in
Microwire bit and pin names. Changed
UART pin names to TXD and RXD. Added
Section 11.6 “Auxiliary Clocks”. Changed
diagram of I/O Port Pin Logic (Section 14).
Major Changes From Previous Version
T3
Fast Read
T1-2
In
T1
DS128