MPC852TZT100 FREESCALE [Freescale Semiconductor, Inc], MPC852TZT100 Datasheet

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MPC852TZT100

Manufacturer Part Number
MPC852TZT100
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Freescale Semiconductor
Technical Data
MPC852T PowerQUICC™
Hardware Specifications
This document contains detailed information for the
MPC852T power considerations, DC/AC electrical
characteristics, AC timing specifications, and pertinent
electrical and physical characteristics. For information about
functional characteristics of the processor, refer to the
MPC866 PowerQUICC™ Family Reference Manual
(MPC866UM). The MPC852T contains a PowerPC™
processor core built on Power Architecture™ technology.
To locate published errata or updates for this document, refer
to the MPC852T product summary page on our website
listed on the back cover of this document or, contact your
local Freescale sales office.
© Freescale Semiconductor, Inc., 2004, 2007. All rights reserved.
10. Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
11. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 42
14. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
15. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 57
16. Mechanical Data and Ordering Information . . . . . . . 60
17. Document Revision History . . . . . . . . . . . . . . . . . . . 76
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
8. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9. Power Supply and Power Sequencing . . . . . . . . . . . 12
Document Number: MPC852TEC
Contents
Rev. 4, 09/2007

Related parts for MPC852TZT100

MPC852TZT100 Summary of contents

Page 1

Freescale Semiconductor Technical Data MPC852T PowerQUICC™ Hardware Specifications This document contains detailed information for the MPC852T power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics. For information about functional characteristics of the processor, refer to ...

Page 2

Overview 1 Overview The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC™ family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V I/O ...

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wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller-programmable to support most size and speed memory interfaces — Four CAS lines, four ...

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Features • Two baud rate generators — Independent (can be connected toany SCC3/4 or SMC1) — Allows changes during operation — Autobaud support option • Two SCCs (serial communication controllers) — Ethernet/IEEE 802.3® standard optional on SCC3 and SCC4, supporting ...

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Instruction Bus Embedded MPC8xx Processor Load/Store Core Bus Fast Ethernet Controller DMAs FIFOs 10/100 Base-T 2 Baud Rate Media Access Control MII MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 4-Kbyte Instruction Cache Unified Instruction MMU Bus 32-Entry ITLB 4-Kbyte ...

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Maximum Tolerated Ratings 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. provides the maximum ratings and operating temperatures. Rating 1 Supply voltage 2 Input voltage Storage temperature range 1 The power ...

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Rating 1 Temperature (standard) Temperature (extended) 1 Minimum temperatures are guaranteed as ambient temperature, T temperature This device contains circuitry protecting against damage that high-static voltage or electrical fields cause; however, Freescale recommends taking normal precautions to ...

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Power Dissipation 5 Power Dissipation Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed. Die Revision Bus Mode 0 1 Typical power ...

Page 9

Table 5. DC Electrical Specifications (continued) Characteristic Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins Input leakage current, Vin = V (Except TMS, TRST, DDH DSCK, and DSDI) Input leakage ...

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Thermal Calculation and Measurement where ambient temperature (º package junction-to-ambient thermal resistance (ºC/W) θ power dissipation in package D The junction-to-ambient thermal resistance is an industry standard value that provides a quick and ...

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If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be ...

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Power Supply and Power Sequencing 9 Power Supply and Power Sequencing This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage (V ) and PLL voltage (V DDL The I/O section of the MPC852T ...

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The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the mandatory value in Table 6 Table 6. Mandatory Reset Configuration of MPC852T Register/Configuration HRCW (Hardware reset configuration word) SIUMCR (SIU module configuration register) MBMR (Machine B ...

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Bus Signal Timing 12 Bus Signal Timing The maximum bus speed that the MPC852T supports is 66 MHz. standard part frequencies. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Frequency Core Bus Table 8. Frequency Ranges ...

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Num Characteristic CLKOUT pulse width high (MIN = 0.4 × B1, B3 MAX = 0.6 × B1) B4 CLKOUT rise time B5 CLKOUT fall time B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 × ...

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Bus Signal Timing Num Characteristic B15 CLKOUT to TEA High-Z (MIN = 0.00 × 2.50) B16 TA, BI valid to CLKOUT (setup time) (MIN = 0.00 × 6.00) B16a TEA, KR, RETRY, CR valid to CLKOUT ...

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Num Characteristic B24a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 × B1 – 2.00) B25 CLKOUT rising edge to OE, WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 × 9.00) B26 CLKOUT ...

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Bus Signal Timing Num Characteristic B29b CS negated to D(0:31), DP(0:3), High Z GPCM write access, ACS = 00, TRLX = 0,1 and CSNT = 0 (MIN = 0.25 × B1 – 2.00) B29c CS negated to D(0:31), DP(0:3) High-Z ...

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Num Characteristic B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == ...

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Bus Signal Timing Num Characteristic B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 × 6.80) B32b CLKOUT rising edge ...

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Num Characteristic B35b A(0:31), BADDR(28:30), and D(0:31 valid - as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 × B1 – 2.00) B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as ...

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Bus Signal Timing Figure 4 is the control timing diagram. CLKOUT B Outputs Outputs Inputs Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 5 ...

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Figure 6 provides the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. ...

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Bus Signal Timing Figure 8 provides the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also ...

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Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) ...

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Bus Signal Timing CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ...

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CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B12 B8 B22a B27 B27a B22b ...

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Bus Signal Timing Figure 15 through Figure 17 provide the timing for the external bus write that various GPCM factors control. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or ...

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CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B28b B28d B22 B25 B26 B28a ...

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Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev B12 B8 B22 B25 B26 B8 ...

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Figure 18 provides the timing for the external bus that the UPM controls. CLKOUT A[0:31] CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B8 B31a B31d B31 B34 ...

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Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the ...

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Figure 21 provides the timing for the synchronous external master access that the GPCM controls. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 22 provides the timing for ...

Page 34

Bus Signal Timing Table 10 provides interrupt timing for the MPC852T. . Num I39 IRQx valid to CLKOUT rising edge (set up time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high I43 ...

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Table 11 shows the PCMCIA timing for the MPC852T. Num Characteristic A(0:31), REG valid to PCMCIA Strobe J82 1 (MIN = 0.75 × B1 – 2.00) asserted. J83 A(0:31), REG valid to ALE negation. (MIN = 1.00 × B1 – ...

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Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 ...

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Figure 27 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS A[0:31] REG CE1/CE2 PCWE, IOWR ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. ...

Page 38

Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC852T. Num Characteristic J95 CLKOUT to OPx Valid (MAX = 0.00 × 19.00) J96 HRESET negated to OPx drive (MIN = 0.75 × 3.00) ...

Page 39

Table 13 shows the debug port timing for the MPC852T. Num Characteristic J82 DSCK cycle time J83 DSCK clock pulse width J84 DSCK rise and fall times J85 DSDI input data setup time J86 DSDI data hold time J87 DSCK ...

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Bus Signal Timing Table 14 shows the reset timing for the MPC852T. Num Characteristic J82 CLKOUT to HRESET high impedance (MAX = 0.00 × 20.00) J83 CLKOUT to SRESET high impedance (MAX = 0.00 × 20.00) ...

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Figure 33 shows the reset timing for the data bus configuration. HRESET RSTCONF D[0:31] (IN) Figure 33. Reset Timing—Configuration from Data Bus Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF D[0:31] ...

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IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 35. Reset Timing—Debug Port Configuration 13 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC852T shown ...

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TCK TCK TMS, TDI TDO Figure 37. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor J82 J83 J82 ...

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CPM Electrical Characteristics 14 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC852T. 14.1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C ...

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IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shown in Num 40 DREQ setup time to clock high 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high 43 SDACK ...

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CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC852T ...

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CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 14.3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Num 50 BRGO rise ...

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CPM Electrical Characteristics 14.4 Timer AC Electrical Specifications Table 19 provides the general-purpose timer timings as shown in Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low ...

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Table 20. NMSI External Clock Timing (continued) Num Characteristic 107 RXD3 hold time from RCLK3 rising edge 108 CD3 setup Time to RCLK3 rising edge 1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1. 2 ...

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CPM Electrical Characteristics Figure 47 through Figure 49 show the NMSI timings. RCLK3 102 106 RxD3 (Input) CD3 (Input) CD3 (SYNC Input) Figure 47. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) ...

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TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Echo Input) 14.6 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Num 120 CLSN width high 121 RCLK3 rise/fall time 122 RCLK3 width low 1 123 RCLK3 clock period ...

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CPM Electrical Characteristics Num 135 RSTRT active delay (from TCLK3 falling edge) 136 RSTRT inactive delay (from TCLK3 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK negated 1 The ratios SyncCLK/RCLK3 ...

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TCLK3 128 131 TxD3 (Output) 133 TENA(RTS3) (Input) RENA(CD3) (Input) (Note 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the ...

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CPM Electrical Characteristics 14.7 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Num 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master ...

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SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI (Output) Figure 56. SPI Master ( Timing Diagram 14.8 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown ...

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CPM Electrical Characteristics SPISEL (Input) SPICLK ( (Input) 173 173 SPICLK ( (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 57. SPI Slave ( Timing Diagram SPISEL (Input) 171 SPICLK (CI ...

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FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL ...

Page 58

FEC Electrical Characteristics Table 26 provides information about the MII transmit signal timing,. Num Characteristic M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low Figure ...

Page 59

MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under ...

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... MPC852T PowerQUICC™ Hardware Specifications, Rev Temperature (Tj) Frequency (MHz) 0°C to 95° 100 –40°C to 100° 100 Order Number MPC852TVR50A MPC852TZT50A MPC852TVR66A MPC852TZT66A MPC852TVR80A MPC852TZT80A MPC852TVR100A MPC852TZT100A MPC852TCVR50A MPC852TCZT50A MPC852TCVR66A MPC852TCZT66A MPC852TCVR80A MPC852TCZT80A MPC852TCVR100A MPC852TCZT100A Freescale Semiconductor ...

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JEDEC Compliant Pinout Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC™ Family Reference Manual. N/C CS1 CS7 GPL_A2 WE2 CS0 WR CE2_A GPL_A3 WE3 ...

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Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 30. Pin Assignments—JEDEC Standard Name A[0:31] B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, ...

Page 63

Table 30. Pin Assignments—JEDEC Standard (continued) Name FRZ H4 IRQ6 IRQ0 P13 IRQ1 M11 M_TX_CLK N12 IRQ7 CS[0:5] B2, A2, D3, C3, E6, C4 CS6 D4 CS7 A3 WE0 D6 BS_B0 IORD WE1 C6 BS_B1 IOWR WE2 A5 BS_B2 PCOE ...

Page 64

Mechanical Data and Ordering Information Table 30. Pin Assignments—JEDEC Standard (continued) Name EXTAL M1 CLKOUT N6 EXTCLK N2 ALE_A H1 CE1_A E5 CE2_A B3 WAIT_A N3 IP_A0 T2 IP_A1 M6 IP_A2, IOIS16_A R3 IP_A3 M5 IP_A4 T3 IP_A5 N5 IP_A6 ...

Page 65

Table 30. Pin Assignments—JEDEC Standard (continued) Name PA3, CLK5, BRGO3, TIN3 K16 PA2, CLK6, TOUT3 K14 PA1, CLK7, BRGO4, TIN4 L15 PA0, CLK8, TOUT4 M16 PB31, SPISEL E13 PB30, SPICLK F13 PB29, SPIMOSI D15 PB28, SPIMISO, BRGO4 G13 PB25, SMTXD1 ...

Page 66

Mechanical Data and Ordering Information Table 30. Pin Assignments—JEDEC Standard (continued) Name PC4, CD4 L14 PD15, MII_RXD3 M14 PD14, MII_RXD2 N16 PD13, MII_RXD1 K13 PD12, MII_MDC N15 PD11, RXD3, MII_TX_ER P16 PD10, TXD3, MII_RXD0 R15 PD9, RXD4, MII_TXD0 N14 PD8, ...

Page 67

Table 30. Pin Assignments—JEDEC Standard (continued) Name MII_MDIO G16 MII_TXEN T14 MII_COL SSSYN V P3 SSSYN1 V P2 DDSYN GND G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, ...

Page 68

Mechanical Data and Ordering Information 16.1.2 The non-JEDEC Pinout Figure 64 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the PowerQUICC™ Family Reference Manual. NOTE: This figure shows the top ...

Page 69

Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Name A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, C13, B13, E12, F10, D12, B10, B12, ...

Page 70

Mechanical Data and Ordering Information Table 31. Pin Assignments—Non-JEDEC (continued) Name BB G4 FRZ, IRQ6 J5 IRQ0 R14 IRQ1 N12 IRQ7, M_TX_CLK P13 CS[0:5] C3, B3, E4, D4, F7, D5 CS6 E5 CS7 B4 WE0, BS_B0, IORD E7 WE1, BS_B1, ...

Page 71

Table 31. Pin Assignments—Non-JEDEC (continued) Name IP_A1 N7 IP_A2, IOIS16_A T4 IP_A3 N6 IP_A4 U4 IP_A5 P6 IP_A6 N8 IP_A7 T3 DSCK J3 IWP[0:1], VFLS[0:1] J4, H2 OP0 L2 OP1 L3 OP2, MODCK1, STS L4 OP3, MODCK2, DSDO M2 BADDR[28:29] ...

Page 72

Mechanical Data and Ordering Information Table 31. Pin Assignments—Non-JEDEC (continued) Name PB31, SPISEL F14 PB30, SPICLK G14 PB29, SPIMOSI E16 PB28, SPIMISO, BRGO4 H14 PB25, SMTXD1 J15 PB24, SMRXD1 J17 PB15, BRGO3 M17 PC15, DREQ0 D17 PC13, RTS3 F15 PC12, ...

Page 73

Table 31. Pin Assignments—Non-JEDEC (continued) Name PD12, MII_MDC P16 PD11, RXD3, MII_TX_ER R17 PD10, TXD3, MII_RXD0 T16 PD9, RXD4, MII_TXD0 P15 PD8, TXD4, MII_RX_CLK N14 PD7, RTS3, MII_RX_ER U16 PD6, RTS4, MII_RX_DV P14 PD5, MII_TXD3 T15 PD4, MII_TXD2 R15 PD3, ...

Page 74

Mechanical Data and Ordering Information Table 31. Pin Assignments—Non-JEDEC (continued) Name V R4 SSSYN1 V R3 DDSYN GND H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9, K10, K11, K12, L7, L8, L9, L10, ...

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Mechanical Dimensions of the PBGA Package For more information on the printed-circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note (order number: AN1231) that is ...

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Document Revision History 17 Document Revision History Table 32 lists significant changes between revisions of this document. Revision Date 4 • Updated template. • On page 1, updated first paragraph and added a second paragraph. • After Table 2, inserted ...

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THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 77 ...

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Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 79 ...

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