PLDC20G10-25JC CYPRESS [Cypress Semiconductor], PLDC20G10-25JC Datasheet
PLDC20G10-25JC
Manufacturer Part Number
PLDC20G10-25JC
Description
CMOS Generic 24-Pin Reprogrammable Logic Device
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.PLDC20G10-25JC.pdf
(14 pages)
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Quantity
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Company:
Part Number:
PLDC20G10-25JC
Manufacturer:
CY
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Cypress Semiconductor Corporation
Document #: 38-03010 Rev. *A
Features
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
• Fast
• Low power
• Commercial and military temperature range
• User-programmable output cells
• Generic architecture to replace standard logic
• Eight product terms and one OE product term per output
— Commercial: t
— Military: t
— I
— I
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or
functions including: 20L10, 20L8, 20R8, 20R6, 20R4,
12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
difference is in the location of the “no connect” or NC pins.
product term
Logic Block Diagram
CC
CC
Pin Configurations
I/OE
V
13
12
SS
max.: 70 mA, commercial
max.: 100 mA, military
NC
I
I
I
I
I
I
PD
5
6
7
8
9
10
11
OUTPUT
I/O
14
11
I
12131415161718
= 20 ns, t
4 3 2
CELL
PLDC20G10B
9
8
PLDC20G10
PD
Top View
LCC
1
= 15 ns, t
282726
OUTPUT
I/O
15
10
CO
I
CELL
8
8
25
24
23
22
21
20
19
= 15 ns, t
CO
NC
I/O
I/O
I/O
I/O
I/O
I/O
4
5
2
3
6
7
= 10 ns, t
OUTPUT
I/O
16
9
I
CELL
8
7
S
•
= 15 ns
CMOS Generic 24-Pin Reprogrammable
S
OUTPUT
I/O
17
8
I
3901 North First Street
CELL
= 12 ns
8
6
NC
NC
NC
USE ULTRA37000™ FOR
ALL NEW DESIGNS
I
I
I
I
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
OUTPUT
I/O
7
PLDC20G10B
I
18
PLDC20G10
CELL
STD PLCC
5
PROGRAMMABLE
8
Top View
AND ARRAY
1
2827 26
Functional Description
Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
OUTPUT
• CMOS EPROM technology for reprogrammability
• Highly reliable
I/O
19
6
I
CELL
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
— ±10% power supply voltage and higher noise
25
24
23
22
21
20
19
8
4
immunity
I/O
I/O
I/O
I/O
I/O
I/O
NC
3
5
7
2
4
6
•
OUTPUT
I/O
5
I
20
CELL
3
8
San Jose
OUTPUT
I/O
NC
21
4
I
CELL
I
I
I
I
I
I
2
8
,
5
6
7
8
9
10
11
CA 95134
121314 1516 1718
4 3 2
JEDEC PLCC
CG7C323B–A
CG7C323–A
OUTPUT
I/O
22
3
Top View
I
CELL
8
1
1
2827 26
Logic Device
Revised April 20, 2004
PLDC20G10B
OUTPUT
I/O
25
24
23
22
21
20
19
23
•
2
I
CELL
PLDC20G10
[1]
8
0
I/O
I/O
I/O
NC
I/O
I/O
I/O
408-943-2600
2
3
4
5
6
7
CP/I
V
24
1
CC
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