ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 18
ADAU1373BCBZ-RL
Manufacturer Part Number
ADAU1373BCBZ-RL
Description
Low Power Codec with Speaker and Headphone Amplifier
Manufacturer
AD [Analog Devices]
Datasheet
1.ADAU1373BCBZ-RL.pdf
(296 pages)
- Current page: 18 of 296
- Download datasheet (9Mb)
ADAU1373
DIGITAL TIMING SPECIFICATIONS
−40°C < T
Table 6.
Parameter
MASTER CLOCK
SERIAL PORT
I
DIGITAL MICROPHONE
2
C PORT
Duty Cycle
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BIL
BIH
LIS
LIH
SIS
SIH
SODM
SCL
SCLH
SCLL
SCS
SCH
DS
DH
SCR
SCF
SDR
SDF
BFT
DCF
DCR
DDV
DDH
A
< +85°C, IOVDDx = 1.8 V ± 10%.
t
45
5
5
5
5
5
5
0.6
1.3
0.6
0.6
100
5
0.6
22
0
MIN
Limit
t
55
50
400
300
300
300
300
10
10
30
12
MAX
Unit
%
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
Rev. 0 | Page 18 of 296
Description
BCLKx pulse width low
BCLKx pulse width high
LRCLKx hold; time from BCLK rising
DAC_SDATA setup; time to BCLK rising
DAC_SDATA hold; time from BCLK rising
ADC_SDATA delay; time from BCLK falling in master mode
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period of time, the first clock is generated
Data hold time
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus-free time; time between stop and start
R
Digital microphone clock fall time
Digital microphone clock rise time
Digital microphone delay time for valid data
Digital microphone delay time for data, three-stated
LRCLKx setup; time to BCLK rising
Data setup time
L
= 1 MΩ, C
L
= 14 pF
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