MC68HC705C4ACB MOTOROLA [Motorola, Inc], MC68HC705C4ACB Datasheet - Page 15
MC68HC705C4ACB
Manufacturer Part Number
MC68HC705C4ACB
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705C4ACB.pdf
(210 pages)
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
MOTOROLA
Technical Data — MC68HC705C4A • MC68HSC705C4A
Figure
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
5-1
Option Register (Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
40-Pin PDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 26
44-Lead PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . 27
44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .27
42-Pin SDIP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 28
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 29
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2-Pin Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . . 31
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 48
External Interrupt Internal Function Diagram . . . . . . . . . . . . 54
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Reset and Interrupt Processing Flowchart . . . . . . . . . . . . . . 62
COP Watchdog Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
List of Figures
Title
List of Figures
Technical Data
Page
15
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