PIC18F24J10-E/ML MICROCHIP [Microchip Technology], PIC18F24J10-E/ML Datasheet - Page 71
![no-image](/images/no-image-200.jpg)
PIC18F24J10-E/ML
Manufacturer Part Number
PIC18F24J10-E/ML
Description
28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F24J10-EML.pdf
(358 pages)
- Current page: 71 of 358
- Download datasheet (6Mb)
REGISTER 6-1:
© 2007 Microchip Technology Inc.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1: DATA EEPROM CONTROL REGISTER 1
bit 7
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to the EEPROM is complete
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
S = Bit can be set by software, but not cleared
-n = Value at POR
U-0
—
(cleared by completion of erase operation)
normal operation, or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
U-0
—
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
R/W-0
FREE
PIC18F45J10 FAMILY
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS39682C-page 69
U-0
—
bit 0
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