PIC18F24J11 MICROCHIP [Microchip Technology], PIC18F24J11 Datasheet - Page 529

• Manufacturer Part Number: PIC18F24J11
• Description: 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

RTCEN Bit Write .............................................................. 239
S
SCKx ................................................................................ 272
SDIx ................................................................................. 272
SDOx ............................................................................... 272
SEC_IDLE Mode ................................................................ 52
SEC_RUN Mode ................................................................ 48
Serial Clock, SCKx ........................................................... 272
Serial Data In (SDIx) ........................................................ 272
Serial Data Out (SDOx) ................................................... 272
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 447
Shoot-Through Current .................................................... 265
Slave Select (SSx) ........................................................... 272
SLEEP ............................................................................. 448
Software Simulator (MPLAB SIM) .................................... 464
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ........................................... 395
SPI Mode (MSSP) ............................................................ 272
SSPOV ............................................................................. 316
SSPOV Status Flag ......................................................... 316
SSPxSTAT Register
SSx .................................................................................. 272
Stack Full/Underflow Resets .............................................. 81
SUBFSR .......................................................................... 459
SUBFWB .......................................................................... 448
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Peripheral Module Disable (PMD) Register ............. 244
Register Interface ..................................................... 239
Register Maps .......................................................... 245
Reset ........................................................................ 244
Value Registers (RTCVAL) ...................................... 233
Associated Registers ............................................... 281
Bus Mode Compatibility ........................................... 280
Clock Speed, Interactions ........................................ 280
Effects of a Reset ..................................................... 280
Enabling SPI I/O ...................................................... 276
Master Mode ............................................................ 277
Master/Slave Connection ......................................... 276
Operation ................................................................. 275
Operation in Power-Managed Modes ...................... 280
Registers .................................................................. 273
Serial Clock .............................................................. 272
Serial Data In ........................................................... 272
Serial Data Out ........................................................ 272
Slave Mode .............................................................. 278
Slave Select ............................................................. 272
Slave Select Synchronization .................................. 278
SPI Clock ................................................................. 277
SSPxBUF Register .................................................. 277
SSPxSR Register ..................................................... 277
Typical Connection .................................................. 276
R/W Bit ............................................................. 296, 299
ALRMVAL Register Mapping ........................... 242
Calibration ........................................................ 242
Clock Source ................................................... 240
Digit Carry Rules .............................................. 240
General Functionality ....................................... 241
Leap Year ........................................................ 241
Register Mapping ............................................. 241
RTCVAL Register Mapping ............................. 242
Safety Window for Register Reads and Writes 241
Write Lock ........................................................ 241
Device .............................................................. 244
Power-on Reset (POR) .................................... 244
Open-Drain Output Option ............................... 275
PIC18F46J11 FAMILY
SUBLW ............................................................................ 449
SUBULNK ........................................................................ 459
SUBWF ............................................................................ 449
SUBWFB ......................................................................... 450
SWAPF ............................................................................ 450
T
Table Pointer Operations with TBLRD, TBLWT (table) ... 106
Table Reads/Table Writes ................................................. 81
T
TBLRD ............................................................................. 451
TBLWT ............................................................................ 452
Timer0 ............................................................................. 197
Timer1 ............................................................................. 201
Timer2 ............................................................................. 213
Timer3 ............................................................................. 215
Timer4 ............................................................................. 225
Timing Diagrams
AD
Associated Registers ............................................... 199
Operation ................................................................. 198
Overflow Interrupt .................................................... 199
Prescaler ................................................................. 199
Prescaler Assignment (PSA Bit) .............................. 199
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 199
Reads and Writes in 16-Bit Mode ............................ 198
Source Edge Select (T0SE Bit) ............................... 198
Source Select (T0CS Bit) ........................................ 198
16-Bit Read/Write Mode .......................................... 206
Associated Registers ............................................... 212
Clock Source Selection ........................................... 204
Gate ......................................................................... 208
Interrupt ................................................................... 207
Operation ................................................................. 204
Oscillator .......................................................... 201, 206
Resetting, Using the ECCP Special Event Trigger .. 208
TMR1H Register ...................................................... 201
TMR1L Register ...................................................... 201
Use as a Clock Source ............................................ 207
Associated Registers ............................................... 214
Interrupt ................................................................... 214
Operation ................................................................. 213
Output ...................................................................... 214
16-Bit Read/Write Mode .......................................... 219
Associated Registers ............................................... 223
Gate ......................................................................... 219
Operation ................................................................. 218
Oscillator .......................................................... 215, 219
Overflow Interrupt ............................................ 215, 223
Special Event Trigger (ECCP) ................................. 223
TMR3H Register ...................................................... 215
TMR3L Register ...................................................... 215
Associated Registers ............................................... 226
Interrupt ................................................................... 226
MSSP Clock Shift .................................................... 226
Operation ................................................................. 225
Output ...................................................................... 226
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 225
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 225
TMR4 to PR4 Match Interrupt .......................... 225, 226
A/D Conversion ....................................................... 506
Asynchronous Reception ......................................... 340
Asynchronous Transmission ................................... 338
.................................................................................. 357
Switching Assignment ..................................... 199
Layout Considerations ..................................... 207
DS39932D-page 529