MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 115

• Manufacturer Part Number: MC68HC705P9CDW
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

9.7.6 Output Compare Registers
MC68HC705P9 — Rev. 4.0
MOTOROLA
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL), the planned TCMP pin
action takes place. Writing to OCRH before writing to OCRL inhibits
timer compares until OCRL is written. Reading or writing to OCRL after
reading the timer status register clears the output compare flag (OCF).
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use the following procedure:
Reset:
Reset:
$0016
$0017
Read:
Read:
Write:
Write:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
Freescale Semiconductor, Inc.
Figure 9-17. Output Compare Registers (OCRH and OCRL)
For More Information On This Product,
Bit 15
Bit 7
Bit 7
Bit 7
Go to: www.freescale.com
14
6
6
6
Timer
13
5
5
5
Unaffected by reset
Unaffected by reset
12
4
4
4
11
3
3
3
10
2
2
2
1
9
1
1
Technical Data
I/O Registers
Bit 0
Bit 8
Bit 0
Bit 0
Timer
115