MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 68
MC68HC705P9CDW
Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC705P9CDW.pdf
(160 pages)
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Resets and Interrupts
5.2.3 COP Watchdog Reset
5.3 Low-Voltage Protection
5.4 Interrupts
Technical Data
68
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of
the COP register at location $1FF0.
A drop in power supply voltage below the minimum operating V
voltage is called a brownout condition. A brownout while the MCU is in a
non-reset state can corrupt MCU operation and necessitate a power-on
reset to resume operation.
The best protection against brownout is an undervoltage sensing circuit
that pulls the RESET pin low when it detects a low-power supply voltage.
The undervoltage sensing circuit may be made of discrete components
or an integrated circuit can be used.
For information about brownout and the COP watchdog, see
Computer Operating Properly Watchdog
The following sources can generate interrupts:
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a user-
defined interrupt vector address.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
SWI instruction
IRQ/V
Capture/compare timer
PP
Go to: www.freescale.com
Resets and Interrupts
pin
(COP).
MC68HC705P9 — Rev. 4.0
Section 8.
MOTOROLA
DD
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