MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 86

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Parallel Input/Output (I/O) Ports
7.4.2 Data Direction Register B (DDRB)
Technical Data
86
NOTE:
NOTE:
SDI — Serial Data Input
SDO — Serial Data Output
Data direction register B determines whether each port B pin is an input
or an output.
Enabling and then disabling the SIOP configures data direction register
B for SIOP operation and can also change the port B data register. After
disabling the SIOP, initialize data direction register B and the port B data
register as your application requires.
DDRB[7:5] — Data Direction Register B Bits
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-7
Reset:
$0005
Read:
Write:
When the SIOP is enabled, SDI is the SIOP data input.
When the SIOP is enabled, SDO is the SIOP data output.
These read/write bits control port B data direction. Reset clears
DDRB[7:5], configuring all three port B pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
DDRB7
Bit 7
0
Parallel Input/Output (I/O) Ports
Figure 7-6. Data Direction Register B (DDRB)
shows the I/O logic of port B.
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= Unimplemented
DDRB6
6
0
DDRB5
5
0
4
0
0
3
0
0
MC68HC705P9 — Rev. 4.0
2
0
0
1
0
0
MOTOROLA
Bit 0
0
0

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