MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 87

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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7.5 Port C
MC68HC705P9 — Rev. 4.0
MOTOROLA
Writing a logic one to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic zero disables the output buffer.
When bit DDRBx is a logic one, reading address $0001 reads the PBx
data latch. When bit DDRBx is a logic zero, reading address $0001
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
operation of the port B pins.
Port C is an 8-bit I/O port that shares five of its pins with the A/D
converter (ADC). The five shared pins are available for general-purpose
I/O functions when the ADC is disabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
READ DATA DIRECTION REGISTER B ($0005)
WRITE DATA DIRECTION REGISTER B ($0005)
WRITE PORT B DATA REGISTER ($0001)
READ PORT B DATA REGISTER ($0001)
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
Data Direction Bit
Parallel Input/Output (I/O) Ports
Go to: www.freescale.com
0
1
Table 7-2. Port B Pin Operation
Figure 7-7. Port B I/O Logic
I/O Pin Mode
Input, Hi-Z
Output
RESET
(1)
DDRBx
PBx
Accesses to Data Bit
Read
Latch
Pin
Parallel Input/Output (I/O) Ports
Table 7-2
Latch
Write
Latch
summarizes the
(2)
Technical Data
Port C
87
PBx

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