AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 174
AT83C51SND1C_03
Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT83C51SND1C_03.pdf
(210 pages)
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Analog to Digital
Converter
Description
174
AT8xC51SND1C
The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital con-
verter (ADC). First channel of this ADC can be used for battery monitoring while the
second one can be used for voice sampling at 8 kHz.
The A/D converter interfaces with the C51 core through four special function registers:
ADCON, the ADC control register (see Table 147); ADDH and ADDL, the ADC data reg-
isters (see Table 149 and Table 150); and ADCLK, the ADC clock register (see
Table 148).
As shown in Figure 129, the ADC is composed of a 10-bit cascaded potentiometric digi-
tal to analog converter, connected to the negative input of a comparator. The output
voltage of this DAC is compared to the analog voltage stored in the Sample and Hold
and coming from AIN0 or AIN1 input depending on the channel selected (see
Table 146). The 10-bit ADDAT converted value (see formula in Figure 129) is delivered
in ADDH and ADDL registers, ADDH is giving the 8 most significant bits while ADDL is
giving the 2 least significant bits. ADDAT
Figure 129. ADC Structure
Figure 130 shows the timing diagram of a complete conversion. For simplicity, the figure
depicts the waveforms in idealized form and do not provide precise timing information.
For ADC characteristics and timing parameters refer to the section “AC Characteristics”.
Figure 130. Timing Diagram
AIN1
AIN0
ADEOC
ADSST
ADEN
CLK
CLOCK
ADC
ADDAT
ADCON.0
ADCS
T
0
1
SETUP
=
1023 V
---------------------------
V
ADCON.5
Sample and Hold
ADEN
REF
⋅
CONTROL
T
IN
ADCLK
AVSS
ADCON.3
ADSST
+
-
T
CONV
AREFP
ADEOC
ADCON.4
R/2R DAC
AREFN
SAR
EADC
IEN1.3
8
2
10
4109E–8051–06/03
ADDH
ADDL
ADC
Interrupt
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