MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 102

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Clock Generator Module (CGM)
Advance Information
102
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. (For maximum immunity guidelines, refer to
document numbers AN1050/D and AN1263/D on electromagnetic
compatibility available from your Motorola sales office.) The VCO
frequency is bound to a range from roughly one-half to twice the
center-of-range frequency, f
pin changes the frequency within this range. By design, f
the nominal center-of-range frequency, f
factor (L) or f
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a crystal frequency, f
through a buffer. The buffer output is the final reference clock,
CGMRDV, running at a frequency equal to f
The VCO’s output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N (see
PLL). The divider’s output is the VCO feedback clock, CGMVDV,
running at a frequency equal to f
Conditions
The phase detector then compares the VCO feedback clock (CGMVDV)
with the final reference clock (CGMRDV). A correction pulse is
generated based on the phase difference between the two signals. The
loop filter then slightly alters the dc voltage on the external capacitor
connected to CGMXFC, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections, depending
on its mode, described in
The value of the external capacitor and the reference frequency
determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
condition based on this comparison.
Clock Generator Module (CGM)
RD
for more information.
NOM
. The circuit determines the mode of the PLL and the lock
.
8.4.2.2 Acquisition and Tracking
VRS
. Modulating the voltage on the CGMXFC
VCLK
/N. See
NOM
RCLK
8.4.2.4 Programming the
, 4.9152 MHz times a linear
RCLK
, and is fed to the PLL
21.9 CGM Operating
MC68HC708AS48
.
VRS
is equal to
MOTOROLA
VCLK
Modes.
Rev. 4.0
is fed

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