MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 103

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.4.2.2 Acquisition and Tracking Modes
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
The PLL filter is manually or automatically configurable into one of two
operating modes:
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
•
•
Acquisition mode — In acquisition mode, the filter can make large
(see
corrections to the VCO. This mode is used at PLL startup or when
the PLL has suffered a severe noise hit and the VCO frequency is
far off the desired frequency. When in acquisition mode, the ACQ
bit is clear in the PLL bandwidth control register (See
Bandwidth Control
Tracking mode — In tracking mode, the filter makes only small
(see
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
Clock Generator Module (CGM)
21.11 CGM Acquisition/Lock Time
21.11 CGM Acquisition/Lock Time
8.6.2 PLL Bandwidth Control
8.4.3 Base Clock Selector
Register.)
8.4.3 Base Clock Selector
Clock Generator Module (CGM)
Information) frequency
Circuit.) The PLL is
Information)
Register.) If PLL
Functional Description
Advance Information
8.6.2 PLL
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