MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 111

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.6 CGM Registers
MC68HC708AS48
MOTOROLA
NOTES:
Addr.
$001C
$001D
$001E
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL Programming Register
PLL Bandwidth Control
PLL Control Register
Register Name
—
Register (PBWC)
See page 112.
See page 114.
See page 116.
Rev. 4.0
(PCTL)
These registers control and monitor operation of the CGM:
Figure 8-4
(PPG)
•
•
•
Figure 8-4. CGM I/O Register Summary
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
PLL control register (PCTL) (See
PLL bandwidth control register (PBWC) (See
Bandwidth Control
PLL programming register (PPG) (See
Register.)
Clock Generator Module (CGM)
is a summary of the CGM registers.
Bit 7
PLLIE
AUTO
MUL7
R
0
0
0
= Reserved
LOCK
MUL6
PLLF
R
R
6
0
0
1
PLLON
Register.)
MUL5
ACQ
5
1
0
1
MUL4
BCS
XLD
4
0
0
0
8.6.1 PLL Control
VRS7
3
R
R
1
1
0
0
0
Clock Generator Module (CGM)
8.6.3 PLL Programming
VRS6
8.6.2 PLL
2
R
R
1
1
0
0
1
Advance Information
VRS5
CGM Registers
Register.)
R
R
1
1
1
0
0
1
Bit 0
VRS4
R
R
1
1
0
0
0
111