MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 118

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clock Generator Module (CGM)
8.8 Special Modes
8.8.1 Wait Mode
8.8.2 Stop Mode
Advance Information
118
NOTE:
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.
Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
The WAIT and STOP instructions put the MCU in low-power standby
modes.
The WAIT instruction does not affect the CGM. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock (CGMVCLK)
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock
(CGMXCLK) divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
Clock Generator Module (CGM)
MC68HC708AS48
MOTOROLA
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Rev. 4.0