MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 134

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

System Integration Module (SIM)
9.4.2.2 Computer Operating Properly (COP) Reset
9.4.2.3 Illegal Opcode Reset
9.4.2.4 Illegal Address Reset
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
Advance Information
134
NOTE:
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG register is at logic 0. (See
Properly
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
A $9E opcode (pre-byte for SP instructions) followed by an $8E opcode
(stop instruction) generates a stop mode recovery reset.
If the stop enable bit, STOP, in the CONFIG register is logic 0, the SIM
treats the STOP instruction as an illegal opcode and causes an illegal
opcode reset.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset.
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the V
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG register are at logic 0. The RST pin
will be held low until the SIM counts 4096 CGMXCLK cycles after V
rises above V
released from reset to allow the reset vector sequence to occur. (See
Section 10. Low-Voltage Inhibit
DD
voltage falls to the V
(COP).)
System Integration Module (SIM)
LVIR
. Another 64 CGMXCLK cycles later, the CPU is
LVII
voltage. The LVI bit in the SIM reset
(LVI).)
Section 13. Computer Operating
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
DD