MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 142

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
System Integration Module (SIM)
9.7.2 Stop Mode
Advance Information
142
Figure 9-13
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the short stop recovery (SSREC) bit in
the CONFIG register ($001F). If SSREC is set, stop recovery is reduced
from the normal delay of 4096 CGMXCLK cycles down to 32. This is
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
CGMXCLK
IAB
IDB
RST
IAB
IDB
$A6
Figure 9-13. Wait Recovery from Interrupt or Break
System Integration Module (SIM)
$A6
Figure 9-14. Wait Recovery from Internal Reset
and
$6E0B
$A6
$6E0B
$A6
Figure 9-14
RST
$A6
$A6
pin or CPU interrupt or break interrupt
$6E0C
CYCLES
$01
show the timing for wait recovery.
32
$00FF
$0B
CYCLES
32
$00FE
$6E
MC68HC708AS48
$00FD
RST VCT H
$00FC
RST VCT L
MOTOROLA
Rev. 4.0

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