MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 151

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
10.4.1 Polled LVI Operation
10.4.2 Forced Reset Operation
MC68HC708AS48
MOTOROLA
Addr.
$FE0F
Register Name
LVI Status Register
Rev. 4.0
(LVISR)
In applications that can operate at V
software can monitor V
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
In applications that require V
LVI resets allows the LVI module to reset the MCU when V
V
must be at logic 0 to enable the LVI module and to enable LVI resets.
LVII
Figure 10-2. LVI I/O Register Summary
level. In the CONFIG register, the LVIPWRD and LVIRSTD bits
Reset:
Read: LVIOUT
Write:
Bit 7
R
R
Low-Voltage Inhibit (LVI)
0
= Reserved
R
6
0
0
DD
by polling the LVIOUT bit. In the CONFIG
5
R
0
0
DD
to remain above the V
DD
R
4
0
0
levels below the V
LVISTOP LVILCK
3
0
Low-Voltage Inhibit (LVI)
2
0
Functional Description
LVII
Advance Information
level, enabling
LVII
DD
R
1
0
0
level,
falls to the
Bit 0
R
0
0
151

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