MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 175

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

13.4.7 COPL (COP Long Timeout)
13.5 COP Control Register
13.6 Interrupts
13.7 Monitor Mode
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Address:
The COPL bit selects the state of the COP long timeout bit (COPL) in the
CONFIG register ($001F). Timeout periods can be 8,176 or 262,128
CGMXCLK cycles. (See
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
DC Electrical
RST pin.
Reset:
Read:
Write:
$FFFF
Computer Operating Properly (COP)
Bit 7
Figure 13-3. COP Control Register (COPCTL)
Characteristics) is present on the
6
5.4 Configuration
5
Low Byte of Reset Vector
Unaffected by Reset
Clear COP Counter
4
Computer Operating Properly (COP)
3
Register.)
DD
+ V
IRQ/V
2
HI
COP Control Register
(see
Advance Information
PP
pin or on the
21.5 5.0 Volt
1
Bit 0
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