MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 182

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
External Interrupt
14.6 IRQ Module During Break Interrupts
14.7 IRQ Status and Control Register
Advance Information
182
NOTE:
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ/V
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
Shows the state of the IRQ interrupt flag
Clears the IRQ interrupt latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ/V
External Interrupt
9.8.3 SIM Break Flag Control
MC68HC708AS48
PP
interrupt pin
Register.)
MOTOROLA
Rev. 4.0
PP
pin.

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