MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 189

no-image

MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
15.3.2 Data Direction Register A
MC68HC708AS48
MOTOROLA
NOTE:
Rev. 4.0
Address:
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 15-4
Reset:
Read:
Write:
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
$0004
Bit 7
0
Figure 15-3. Data Direction Register A (DDRA)
shows the port A I/O logic.
Input/Output (I/O) Ports
DDRA6
6
0
Figure 15-4. Port A I/O Circuit
RESET
DDRA5
5
0
DDRA4
DDRAx
4
0
PTAx
DDRA3
3
0
DDRA2
2
0
Input/Output (I/O) Ports
Advance Information
DDRA1
1
0
DDRA0
Bit 0
Port A
0
PTAx
189

Related parts for MC68HC708AS48