MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 195

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

15.5.2 Data Direction Register C
MC68HC708AS48
MOTOROLA
NOTE:
NOTE:
—
Rev. 4.0
Address:
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer
for the corresponding port C pin; a logic 0 disables the output buffer.
MCLKEN — MCLK Enable Bit
DDRC[5:0] — Data Direction Register C Bits
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
DDRC is available only in the 64-pin QFP package.
Figure 15-10
Reset:
Read:
Write:
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = MCLK output enabled
0 = MCLK output disabled
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
MCLKEN
$0006
Bit 7
R
0
Figure 15-9. Data Direction Register C (DDRC)
shows the port C I/O logic.
Input/Output (I/O) Ports
= Reserved
R
6
0
0
DDRC5
5
0
DDRC4
4
0
DDRC3
3
0
DDRC2
2
0
Input/Output (I/O) Ports
Advance Information
DDRC1
1
0
DDRC0
Bit 0
Port C
0
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