MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 199

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

15.6.2 Data Direction Register D
MC68HC708AS48
MOTOROLA
NOTE:
NOTE:
—
Rev. 4.0
Address:
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:3, 1:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
DDRD7 is available only in the 64-pin QFP package.
Figure 15-13
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[7:3, 1:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 15-12. Data Direction Register D (DDRD)
R
0
shows the port D I/O logic PTD[7:3, 1:0].
Input/Output (I/O) Ports
= Reserved
DDRD6
6
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
R
2
0
0
Input/Output (I/O) Ports
Advance Information
DDRD1
1
0
DDRD0
Bit 0
Port D
0
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