MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 219

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

16.4.3.2 Buffered Output Compare
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the PTE2/TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (0 or 1) that control
the output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
PTE2/TCH0, is available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TCH2 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2)
links channel 2 and channel 3. The output compare value in the TIM
channel 2 registers initially controls the output on the PTF0/TCH2 pin.
Writing to the TIM channel 3 registers enables the TIM channel 3
registers to synchronously control the output after the TIM overflows. At
each subsequent overflow, the TIM channel registers (2 or 3) that control
the output are the ones written to last. TSC2 controls and monitors the
buffered output compare function, and TIM channel 3 status and control
register (TSC3) is unused. While the MS2B bit is set, the channel 3 pin,
PTF1/TCH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2/TCH4 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4)
links channel 4 and channel 5. The output compare value in the TIM
channel 4 registers initially controls the output on the PTF2/TCH4 pin.
Writing to the TIM channel 5 registers enables the TIM channel 5
Timer Interface (TIM)
Functional Description
Timer Interface (TIM)
Advance Information
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