MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 235

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
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Rev. 4.0
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
When CHxIE = 0, clear CHxF by reading TIM channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupts on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0, TIM channel 2, and TIM
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3 to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TCH5 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
Timer Interface (TIM)
Timer Interface (TIM)
Advance Information
I/O Registers
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