MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 263



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FREESCALE [Freescale Semiconductor, Inc]
17.6 Low-Power Modes
17.6.1 Wait Mode
17.6.2 Stop Mode
17.7 SCI During Break Module Interrupts
Rev. 4.0
The WAIT and STOP instructions put the MCU in low-power standby
The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during interrupts generated by the break
module. The BCFE bit in the SIM break flag control register (SBFCR)
enables software to clear status bits during the break state.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic z0ero to the
BCFE bit. With BCFE at logic 0 (its default state), software can read and
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
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Low-Power Modes

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