MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 290



Manufacturer Part Number
Advance Information
FREESCALE [Freescale Semiconductor, Inc]
Serial Peripheral Interface (SPI)
18.6 Transmission Formats
18.6.1 Clock Phase and Polarity Controls
Advance Information
Data written to the slave shift register during a a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
To prevent SPSCK from appearing as a clock edge, SPSCK must be in
the proper idle state before the slave is enabled.
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock line
synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave
devices that are not selected do not interfere with SPI bus activities. On
a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
Software can select any of four combinations of serial clock (SCK) phase
and polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two
fundamentally different transmission formats. The clock phase and
polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are
changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI
by clearing the SPI enable bit (SPE).
Serial Peripheral Interface (SPI)
18.6 Transmission
Rev. 4.0

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