MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 294



Manufacturer Part Number
Advance Information
FREESCALE [Freescale Semiconductor, Inc]
Serial Peripheral Interface (SPI)
18.6.4 Transmission Initiation Latency
Advance Information
When the SPI is configured as a master (SPMSTR = 1), transmissions
are started by a software write to the SPDR ($0012). CPHA has no effect
on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains
inactive for the first half of the first SCK cycle. When CPHA = 1, the first
SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the
delay from the write to SPDR and the start of the SPI transmission. (See
derivative of the internal MCU clock. It is only enabled when both the
SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges
occur halfway through the low time of the internal MCU clock. Since the
SPI clock is free-running, it is uncertain where the write to the SPDR will
occur relative to the slower SCK. This uncertainty causes the variation
in the initiation delay shown in
than a single SPI bit time. That is, the maximum delay between the write
to SPDR and the start of the SPI transmission is two MCU bus cycles for
DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and
128 MCU bus cycles for DIV128.
18-7.) The internal SPI clock in the master is a free-running
Serial Peripheral Interface (SPI)
18-7. This delay will be no longer
Rev. 4.0

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