MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 313

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Address:
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
OVRF — Overflow Bit
Reset:
Read:
Write:
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
Figure 18-14. SPI Status and Control Register (SPSCR)
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
1 = Overflow
0 = No overflow
$0011
SPRF
Bit 7
R
R
0
Serial Peripheral Interface (SPI)
= Reserved
ERRIE
6
0
OVRF
R
5
0
MODF
R
4
0
SPTE
R
3
1
Serial Peripheral Interface (SPI)
MODFEN
2
0
Advance Information
SPR1
1
0
I/O Registers
SPR0
Bit 0
0
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