MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 321

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

19.4.4 Continuous Conversion
19.4.5 Accuracy and Precision
19.5 Interrupts
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
the conversion to wait until the next rising edge of the ADC internal clock.
With a 1 MHz ADC internal clock the maximum sample rate is 59 kHz to
62 kHz. Refer to
In the continuous conversion mode the ADC continuously converts the
selected channel, filling the ADC data register with new data after each
conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADC status control register,
$0038) is set after each conversion and can be cleared by writing the
ADC status and control register or reading of the ADC data register.
The conversion process is monotonic and has no missing codes. See
21.7 ADC Characteristics
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
Number of Bus Cycles = Conversion Time x Bus Frequency
Conversion Time =
Analog-to-Digital Converter (ADC)
21.7 ADC
16 to 17 ADC Clock Cycles
Characteristics.
for accuracy information.
ADC Clock Frequency
Analog-to-Digital Converter (ADC)
Advance Information
Interrupts
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