MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 332

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
20.4 Functional Description
Advance Information
332
NOTE:
Figure 20-1
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC08AS20 specification.
.
Byte Data Link Controller–Digital (BDLC–D)
shows the organization of the BDLC module. The CPU
Figure 20-1. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
BDLC
MC68HC708AS48
MOTOROLA
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Rev. 4.0