MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 336

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
20.4.1.5 BDLC Stop Mode
20.4.1.6 Digital Loopback Mode
20.4.1.7 Analog Loopback Mode
Advance Information
336
the BDLC receives a valid end-of-frame (EOF) symbol while operating in
wait mode, then the BDLC also will generate a CPU interrupt request,
which wakes up the BDLC and the CPU. See
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 ($003E) is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD)
and the receive digital input pin (BDRxD) of the digital interface are
disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own
messages without driving the J1850 bus.
Analog loopback mode is used to determine if a bus fault has been
caused by a failure in the node’s off-chip analog transceiver or
elsewhere in the network. The BCLD analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does,
however, ensure that once analog loopback mode is exited, the BDLC
will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a
loopback mode, it usually causes the input to the output drive stage to
be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output
Byte Data Link Controller–Digital (BDLC–D)
20.8.1 Wait
MC68HC708AS48
20.8.2 Stop
Mode.
MOTOROLA
—
Rev. 4.0
Mode.