MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 340
MC68HC708AS48
Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
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Byte Data Link Controller–Digital (BDLC–D)
20.5.2 J1850 Frame Format
Advance Information
340
IDLE
SOF
PRIORITY
(DATA0)
Figure 20-6. J1850 Bus Message Format (VPW)
DATA
All messages transmitted on the J1850 bus are structured using the
format shown in
J1850 states that each message has a maximum length of 101 PWM bit
times or 12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each
byte transmitted most significant bit (MSB) first.
All VPW symbol lengths described here are typical values at a 10.4-kbps
bit rate.
SOF — Start-of-Frame Symbol
Data — In-Message Data Bytes
All messages transmitted onto the J1850 bus must begin with a
long-active 200 s period SOF symbol. This indicates the start of a
new message transmission. The SOF symbol is not used in the CRC
calculation.
The data bytes contained in the message include the message
priority/type, message ID byte (typically the physical address of the
responder), and any actual data being transmitted to the receiving
node. The message format used by the BDLC is similar to the 3-byte
consolidated header message format outlined by the SAE J1850
document. See SAE J1850 Class B Data Communications Network
Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain
at least one data byte, and, therefore, can be as short as one data
byte and one CRC byte. Each data byte in the message is eight bits
in length and is transmitted MSB to LSB (least significant bit).
MESSAGE ID
(DATA1)
Byte Data Link Controller–Digital (BDLC–D)
Figure
DATA
20-6.
N
CRC
E
O
D
N
B
OPTIONAL
MC68HC708AS48
IFR
EOF
MOTOROLA
—
F
S
I
Rev. 4.0
IDLE
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